[Quantal,SRU] drm/i915: Use the correct size of the GTT for placing the, per-process entries

Message ID 51780988.2040905@canonical.com
State New
Headers show

Commit Message

Chris J Arges April 24, 2013, 4:34 p.m.
On 04/24/2013 11:07 AM, Chris J Arges wrote:
> BugLink: http://bugs.launchpad.net/bugs/1107642
> SRU Justification:
> Impact:
>     When installing 32-bit images on an imac 12,1 with intel/ati
> graphics, there may be crashes or blank screens.
> Fix:
>    bb588820ef421c6098dca1fec29c3b347f1c8c19 fixes the radeon blackout
> issues; this is already in raring/quantal
>    9a0f938bde74bf9e50bd75c8de9e38c1787398cd fixes the i915 issues. This
> is in raring, but not in quantal.
> Testcase:
>     Update kernel on install iso, and try to install 32-bit ubuntu on
> imac 12,1.
> --chris j arges

Patch attached.


Seth Forshee April 24, 2013, 5:42 p.m. | #1


From afdab184ce86c3cad860cefe9f58eb69066d175b Mon Sep 17 00:00:00 2001
From: Chris Wilson <chris@chris-wilson.co.uk>
Date: Fri, 24 Aug 2012 09:12:22 +0100
Subject: [PATCH] drm/i915: Use the correct size of the GTT for placing the
 per-process entries

BugLink: http://bugs.launchpad.net/bugs/1107642

The current layout is to place the per-process tables at the end of the
GTT. However, this is currently using a hardcoded maximum size for the GTT
and not taking in account limitations imposed by the BIOS. Use the value
for the total number of entries allocated in the table as provided by
the configuration registers.

Reported-by: Matthew Garrett <mjg@redhat.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ben Widawsky <ben@bwidawsk.net>
Cc: Matthew Garret <mjg@redhat.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
(cherry picked from commit 9a0f938bde74bf9e50bd75c8de9e38c1787398cd)

Signed-off-by: Chris J Arges <chris.j.arges@canonical.com>
 drivers/gpu/drm/i915/i915_gem_gtt.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index eae804d..8096d577 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -72,7 +72,7 @@  int i915_gem_init_aliasing_ppgtt(struct drm_device *dev)
 	/* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024
 	 * entries. For aliasing ppgtt support we just steal them at the end for
 	 * now. */
-	first_pd_entry_in_global_pt = 512*1024 - I915_PPGTT_PD_ENTRIES;
+	first_pd_entry_in_global_pt = dev_priv->mm.gtt->gtt_total_entries - I915_PPGTT_PD_ENTRIES;
 	ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
 	if (!ppgtt)