From patchwork Tue Apr 23 20:46:37 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 239000 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id B89A62C0121 for ; Wed, 24 Apr 2013 06:52:08 +1000 (EST) Received: from localhost ([::1]:47004 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UUkC7-0007RY-16 for incoming@patchwork.ozlabs.org; Tue, 23 Apr 2013 16:52:07 -0400 Received: from eggs.gnu.org ([208.118.235.92]:48662) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UUk7M-0001W5-DE for qemu-devel@nongnu.org; Tue, 23 Apr 2013 16:47:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UUk7J-0003fo-Ot for qemu-devel@nongnu.org; Tue, 23 Apr 2013 16:47:12 -0400 Received: from mail-wg0-x22d.google.com ([2a00:1450:400c:c00::22d]:64958) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UUk7J-0003fZ-Fr for qemu-devel@nongnu.org; Tue, 23 Apr 2013 16:47:09 -0400 Received: by mail-wg0-f45.google.com with SMTP id l18so518750wgh.12 for ; Tue, 23 Apr 2013 13:47:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=3T8+LQjxDo/kodzLCQYnwTtsCCvfJkWdosORjAD20IE=; b=GVMMTPojxW9JPraErhOm2kpZ21aRYUXKyLcPC0EfHTlS+fNUs9AQmkDO1W2I+WBHiV /1jsP81d936rnRt9zutqHzx6QsjrTwIih8oCEZRJIbqu7PTTxkePTIxJKJBMrrZezvlV TuheOGRA3B0mi263/6SCFr8bLzcapG3+ulUpZjmfel8xd9ShPteSB3Y4AO/RXU6CIwR5 ovng2qib3C29FsKseKCvllXdYQCx30GpAMiiBci/aiV5EQNF9QTpLXsoT26sc9S6sVbt nN4mdFUXmv1qKyIgSUBbNMPWlYVnWKaVLyoKgoTpYNSmZ2nJbx/gH96oILC3HsoZ8Gkh QDKA== X-Received: by 10.194.176.195 with SMTP id ck3mr42577707wjc.5.1366750028704; Tue, 23 Apr 2013 13:47:08 -0700 (PDT) Received: from fremont.twiddle.net ([212.183.132.78]) by mx.google.com with ESMTPS id q20sm18463501wiv.7.2013.04.23.13.47.07 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 23 Apr 2013 13:47:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 23 Apr 2013 13:46:37 -0700 Message-Id: <1366750012-25015-6-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1366750012-25015-1-git-send-email-rth@twiddle.net> References: <1366750012-25015-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2a00:1450:400c:c00::22d Cc: aurelien@aurel32.net Subject: [Qemu-devel] [PATCH v6 05/20] tcg-arm: Allow constant first argument to sub X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This allows the generation of RSB instructions. Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c index de8465b..6c7113b 100644 --- a/tcg/arm/tcg-target.c +++ b/tcg/arm/tcg-target.c @@ -1625,8 +1625,17 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, args[0], args[1], args[2], const_args[2]); break; case INDEX_op_sub_i32: - tcg_out_dat_rIN(s, COND_AL, ARITH_SUB, ARITH_ADD, - args[0], args[1], args[2], const_args[2]); + if (const_args[1]) { + if (const_args[2]) { + tcg_out_movi32(s, COND_AL, args[0], args[1] - args[2]); + } else { + tcg_out_dat_rI(s, COND_AL, ARITH_RSB, + args[0], args[2], args[1], 1); + } + } else { + tcg_out_dat_rIN(s, COND_AL, ARITH_SUB, ARITH_ADD, + args[0], args[1], args[2], const_args[2]); + } break; case INDEX_op_and_i32: tcg_out_dat_rIK(s, COND_AL, ARITH_AND, ARITH_BIC, @@ -1819,7 +1828,7 @@ static const TCGTargetOpDef arm_op_defs[] = { /* TODO: "r", "r", "ri" */ { INDEX_op_add_i32, { "r", "r", "rIN" } }, - { INDEX_op_sub_i32, { "r", "r", "rIN" } }, + { INDEX_op_sub_i32, { "r", "rI", "rIN" } }, { INDEX_op_mul_i32, { "r", "r", "r" } }, { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } }, { INDEX_op_muls2_i32, { "r", "r", "r", "r" } },