From patchwork Tue Apr 23 20:46:38 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 238997 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id AEE532C0122 for ; Wed, 24 Apr 2013 06:47:57 +1000 (EST) Received: from localhost ([::1]:36764 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UUk83-0001iY-TM for incoming@patchwork.ozlabs.org; Tue, 23 Apr 2013 16:47:55 -0400 Received: from eggs.gnu.org ([208.118.235.92]:48682) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UUk7O-0001ZC-9K for qemu-devel@nongnu.org; Tue, 23 Apr 2013 16:47:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UUk7L-0003gS-Jq for qemu-devel@nongnu.org; Tue, 23 Apr 2013 16:47:14 -0400 Received: from mail-we0-x235.google.com ([2a00:1450:400c:c03::235]:56186) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UUk7L-0003gF-BC for qemu-devel@nongnu.org; Tue, 23 Apr 2013 16:47:11 -0400 Received: by mail-we0-f181.google.com with SMTP id m1so1016443wea.40 for ; Tue, 23 Apr 2013 13:47:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=5RpMbZLVnHs//kmcpxZ3D4uMO9A3XsAfqhzy9+1SqDY=; b=HnsNKxxuxB1Zke9p6yvvnfK/srrbsDkM1UbVgTjmR0ETtzNmcORkMFVpV1LBZ6o1ce HS28ywhtrTOd+bhlLbQmfxNvob17Z9wJx5UriUc6YF1T7ZvzqeR0KuvyonEPe0TLEgxz w1dSjREQZ4XwoaeuBAdu7AIxxFZ3+B87q4lz7SWCPgWZ3rP8ro5ZexUzDt57ZzoSOgT/ 2oSLhRiVkflFOPtdMoUadLfTud/ixPuyNXpTGzpjKbeNuihgSEka2Ia2EWFCMdYdf8us z3F+B5ikrxH444+CjEHvHBD1buwPVxwKNWgiEuj800by+J0yqG9khttT3GDXeHj1TIei v2pA== X-Received: by 10.180.91.106 with SMTP id cd10mr62583250wib.6.1366750030488; Tue, 23 Apr 2013 13:47:10 -0700 (PDT) Received: from fremont.twiddle.net ([212.183.132.78]) by mx.google.com with ESMTPS id q20sm18463501wiv.7.2013.04.23.13.47.08 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 23 Apr 2013 13:47:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 23 Apr 2013 13:46:38 -0700 Message-Id: <1366750012-25015-7-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1366750012-25015-1-git-send-email-rth@twiddle.net> References: <1366750012-25015-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2a00:1450:400c:c03::235 Cc: aurelien@aurel32.net Subject: [Qemu-devel] [PATCH v6 06/20] tcg-arm: Use tcg_out_dat_rIN for compares X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This allows us to emit CMN instructions. Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c | 40 ++++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c index 6c7113b..961b02c 100644 --- a/tcg/arm/tcg-target.c +++ b/tcg/arm/tcg-target.c @@ -1615,10 +1615,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, /* Constraints mean that v2 is always in the same register as dest, * so we only need to do "if condition passed, move v1 to dest". */ - tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, - args[1], args[2], const_args[2]); - tcg_out_dat_rI(s, tcg_cond_to_arm_cond[args[5]], - ARITH_MOV, args[0], 0, args[3], const_args[3]); + tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, + args[1], args[2], const_args[2]); + tcg_out_dat_rIK(s, tcg_cond_to_arm_cond[args[5]], ARITH_MOV, + ARITH_MVN, args[0], 0, args[3], const_args[3]); break; case INDEX_op_add_i32: tcg_out_dat_rIN(s, COND_AL, ARITH_ADD, ARITH_SUB, @@ -1715,7 +1715,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_brcond_i32: - tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, + tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, args[0], args[1], const_args[1]); tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[2]], args[3]); break; @@ -1728,15 +1728,15 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, * TCG_COND_LE(U) --> (a0 <= a2 && a1 == a3) || (a1 <= a3 && a1 != a3), * TCG_COND_GT(U) --> (a0 > a2 && a1 == a3) || a1 > a3, */ - tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, - args[1], args[3], SHIFT_IMM_LSL(0)); - tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, - args[0], args[2], SHIFT_IMM_LSL(0)); + tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, + args[1], args[3], const_args[3]); + tcg_out_dat_rIN(s, COND_EQ, ARITH_CMP, ARITH_CMN, 0, + args[0], args[2], const_args[2]); tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[4]], args[5]); break; case INDEX_op_setcond_i32: - tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, - args[1], args[2], const_args[2]); + tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, + args[1], args[2], const_args[2]); tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[3]], ARITH_MOV, args[0], 0, 1); tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[3])], @@ -1744,10 +1744,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_setcond2_i32: /* See brcond2_i32 comment */ - tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, - args[2], args[4], SHIFT_IMM_LSL(0)); - tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, - args[1], args[3], SHIFT_IMM_LSL(0)); + tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, + args[2], args[4], const_args[4]); + tcg_out_dat_rIN(s, COND_EQ, ARITH_CMP, ARITH_CMN, 0, + args[1], args[3], const_args[3]); tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[5]], ARITH_MOV, args[0], 0, 1); tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[5])], @@ -1845,15 +1845,15 @@ static const TCGTargetOpDef arm_op_defs[] = { { INDEX_op_rotl_i32, { "r", "r", "ri" } }, { INDEX_op_rotr_i32, { "r", "r", "ri" } }, - { INDEX_op_brcond_i32, { "r", "rI" } }, - { INDEX_op_setcond_i32, { "r", "r", "rI" } }, - { INDEX_op_movcond_i32, { "r", "r", "rI", "rI", "0" } }, + { INDEX_op_brcond_i32, { "r", "rIN" } }, + { INDEX_op_setcond_i32, { "r", "r", "rIN" } }, + { INDEX_op_movcond_i32, { "r", "r", "rIN", "rIK", "0" } }, /* TODO: "r", "r", "r", "r", "ri", "ri" */ { INDEX_op_add2_i32, { "r", "r", "r", "r", "r", "r" } }, { INDEX_op_sub2_i32, { "r", "r", "r", "r", "r", "r" } }, - { INDEX_op_brcond2_i32, { "r", "r", "r", "r" } }, - { INDEX_op_setcond2_i32, { "r", "r", "r", "r", "r" } }, + { INDEX_op_brcond2_i32, { "r", "r", "rIN", "rIN" } }, + { INDEX_op_setcond2_i32, { "r", "r", "r", "rIN", "rIN" } }, #if TARGET_LONG_BITS == 32 { INDEX_op_qemu_ld8u, { "r", "l" } },