From patchwork Tue Apr 23 20:46:36 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 238996 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 11EC82C0121 for ; Wed, 24 Apr 2013 06:47:54 +1000 (EST) Received: from localhost ([::1]:36544 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UUk80-0001a8-1R for incoming@patchwork.ozlabs.org; Tue, 23 Apr 2013 16:47:52 -0400 Received: from eggs.gnu.org ([208.118.235.92]:48649) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UUk7K-0001TP-Rv for qemu-devel@nongnu.org; Tue, 23 Apr 2013 16:47:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UUk7I-0003f4-3f for qemu-devel@nongnu.org; Tue, 23 Apr 2013 16:47:10 -0400 Received: from mail-wi0-x231.google.com ([2a00:1450:400c:c05::231]:62571) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UUk7H-0003dZ-Te for qemu-devel@nongnu.org; Tue, 23 Apr 2013 16:47:08 -0400 Received: by mail-wi0-f177.google.com with SMTP id hj19so1338652wib.4 for ; Tue, 23 Apr 2013 13:47:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=6Bq/sgw/1oR/qJBeGLyTwqGbHqpIbWNcNeoDqJafvSg=; b=qZA9744n3ZISsMHSDHba0xY57CkflRGSIy5SSyeT2d6pLyY9hcMhJRTt7HJNSqocMY Vy2CsViDBiQoA4dVNlPjQH3eaQHK1dcN3wKnCPrDboG8UOFZUI9/fniOLjtnQ6x7K2yX tnJisU9t08vN2xXtliFJX0X1WuRiNjNZ9JfUteia0B3z1s4LYf1PNMCGbsNltWjvwFfb Hurt1p8f+jREUfIcQduuCA/JBOOnIzSItYN6BQCyqNTZ4F0fTOgwF4yNBuOVUqj5/UHt 9xkQq6EM0xGW/ZZGEKBSQpvIXCCt+OIUPq3hI+1n9ukHKEtfZgvn7P6AWkHHT8Yidn+s UbAw== X-Received: by 10.180.183.197 with SMTP id eo5mr21327998wic.28.1366750027152; Tue, 23 Apr 2013 13:47:07 -0700 (PDT) Received: from fremont.twiddle.net ([212.183.132.78]) by mx.google.com with ESMTPS id q20sm18463501wiv.7.2013.04.23.13.47.05 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 23 Apr 2013 13:47:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 23 Apr 2013 13:46:36 -0700 Message-Id: <1366750012-25015-5-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1366750012-25015-1-git-send-email-rth@twiddle.net> References: <1366750012-25015-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2a00:1450:400c:c05::231 Cc: aurelien@aurel32.net Subject: [Qemu-devel] [PATCH v6 04/20] tcg-arm: Handle negated constant arguments to and/sub X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This greatly improves code generation for addition of small negative constants. Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c | 41 +++++++++++++++++++++++++++++++++++------ 1 file changed, 35 insertions(+), 6 deletions(-) diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c index 886252f..de8465b 100644 --- a/tcg/arm/tcg-target.c +++ b/tcg/arm/tcg-target.c @@ -147,6 +147,7 @@ static void patch_reloc(uint8_t *code_ptr, int type, #define TCG_CT_CONST_ARM 0x100 #define TCG_CT_CONST_INV 0x200 +#define TCG_CT_CONST_NEG 0x400 /* parse target specific constraints */ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str) @@ -161,6 +162,9 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str) case 'K': ct->ct |= TCG_CT_CONST_INV; break; + case 'N': /* The gcc constraint letter is L, already used here. */ + ct->ct |= TCG_CT_CONST_NEG; + break; case 'r': ct->ct |= TCG_CT_REG; @@ -291,6 +295,8 @@ static inline int tcg_target_const_match(tcg_target_long val, return 1; } else if ((ct & TCG_CT_CONST_INV) && check_fit_imm(~val)) { return 1; + } else if ((ct & TCG_CT_CONST_NEG) && check_fit_imm(-val)) { + return 1; } else { return 0; } @@ -512,6 +518,27 @@ static void tcg_out_dat_rIK(TCGContext *s, int cond, int opc, int opinv, } } +static void tcg_out_dat_rIN(TCGContext *s, int cond, int opc, int opneg, + TCGArg dst, TCGArg lhs, TCGArg rhs, + bool rhs_is_const) +{ + /* Emit either the reg,imm or reg,reg form of a data-processing insn. + * rhs must satisfy the "rIN" constraint. + */ + if (rhs_is_const) { + int rot = encode_imm(rhs); + if (rot < 0) { + rhs = -rhs; + rot = encode_imm(rhs); + assert(rot >= 0); + opc = opneg; + } + tcg_out_dat_imm(s, cond, opc, dst, lhs, rotl(rhs, rot) | (rot << 7)); + } else { + tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); + } +} + static inline void tcg_out_mul32(TCGContext *s, int cond, int rd, int rs, int rm) { @@ -1594,11 +1621,13 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, ARITH_MOV, args[0], 0, args[3], const_args[3]); break; case INDEX_op_add_i32: - c = ARITH_ADD; - goto gen_arith; + tcg_out_dat_rIN(s, COND_AL, ARITH_ADD, ARITH_SUB, + args[0], args[1], args[2], const_args[2]); + break; case INDEX_op_sub_i32: - c = ARITH_SUB; - goto gen_arith; + tcg_out_dat_rIN(s, COND_AL, ARITH_SUB, ARITH_ADD, + args[0], args[1], args[2], const_args[2]); + break; case INDEX_op_and_i32: tcg_out_dat_rIK(s, COND_AL, ARITH_AND, ARITH_BIC, args[0], args[1], args[2], const_args[2]); @@ -1789,8 +1818,8 @@ static const TCGTargetOpDef arm_op_defs[] = { { INDEX_op_st_i32, { "r", "r" } }, /* TODO: "r", "r", "ri" */ - { INDEX_op_add_i32, { "r", "r", "rI" } }, - { INDEX_op_sub_i32, { "r", "r", "rI" } }, + { INDEX_op_add_i32, { "r", "r", "rIN" } }, + { INDEX_op_sub_i32, { "r", "r", "rIN" } }, { INDEX_op_mul_i32, { "r", "r", "r" } }, { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } }, { INDEX_op_muls2_i32, { "r", "r", "r", "r" } },