From patchwork Tue Apr 23 16:37:50 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greta Yorsh X-Patchwork-Id: 238961 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "localhost", Issuer "www.qmailtoaster.com" (not verified)) by ozlabs.org (Postfix) with ESMTPS id A9ED62C00F1 for ; Wed, 24 Apr 2013 02:38:13 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:references:in-reply-to:subject:date:message-id :mime-version:content-type; q=dns; s=default; b=rPcRHHvKSGZnaab1 yUJUoZNQZG9Yf/5MNtI0WVL9M/jtbDJrdj6yCclQh0EftF5HG7kr8Sa6vFuMv4Pp zm0SyiZCa0Ig19Xqitp4BAxuZ9eipotqk3A10yLDd4izicw4H682l9ECpTzcM7Em 7JGJeV1HzBx8c8U171y+o0u0M4c= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:references:in-reply-to:subject:date:message-id :mime-version:content-type; s=default; bh=/BaSyIJUSKrAe18yO9rvJu Woafw=; b=wP+B74lP+Kb4f/tnkcxMpk76kibzU9vKj4cHd37HeoOdEFJzd03q1G N0sxPnnmStLJlhwlz+bP+Lwgb3ePjXdy38LUBQS1a05FEQQHPwWXamGbMkuQ3fkV KZyM6g86pkHokb4sdeQpgEyUTG3mfOVNKjCi59Jncgb1ooVZx/4Dg= Received: (qmail 29253 invoked by alias); 23 Apr 2013 16:38:06 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 29242 invoked by uid 89); 23 Apr 2013 16:38:05 -0000 X-Spam-SWARE-Status: No, score=-2.6 required=5.0 tests=AWL, BAYES_00, KHOP_THREADED, MSGID_MULTIPLE_AT, RCVD_IN_DNSWL_LOW, SPF_PASS, TW_QE autolearn=ham version=3.3.1 Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Tue, 23 Apr 2013 16:38:02 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Tue, 23 Apr 2013 17:37:59 +0100 Received: from e103227vm ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.0); Tue, 23 Apr 2013 17:37:58 +0100 From: "Greta Yorsh" To: "Richard Earnshaw" Cc: "GCC Patches" , , "Ramana Radhakrishnan" References: <000801ce3ce1$23fbdd60$6bf39820$@yorsh@arm.com> <51712BB4.7010608@arm.com> In-Reply-To: <51712BB4.7010608@arm.com> Subject: RE: [PATCH, ARM] Fix PR56797 Date: Tue, 23 Apr 2013 17:37:50 +0100 Message-ID: <000c01ce4040$e548c840$afda58c0$@yorsh@arm.com> MIME-Version: 1.0 X-MC-Unique: 113042317375904801 X-Virus-Found: No Ok to backport to gcc4.8? I'm attaching an updated version - just fixed a spelling error in the comment. Thanks, Greta gcc/ChangeLog PR target/56797 * config/arm/arm.c (load_multiple_sequence): Require SP as base register for loads if SP is in the register list. > -----Original Message----- > From: Richard Earnshaw > Sent: 19 April 2013 12:34 > To: Greta Yorsh > Cc: GCC Patches; raj.khem@gmail.com; Ramana Radhakrishnan > Subject: Re: [PATCH, ARM] Fix PR56797 > > On 19/04/13 10:34, Greta Yorsh wrote: > > Fix PR56797 > > http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56797 > > > > The problem is that peephole optimizer thinks it can generate an ldm, > but > > the pattern for ldm no longer matches, because after r188738 it > requires > > that if one of the destination registers is SP then the base register > must > > be SP, and it's not SP in the test case. > > > > The test case fails on armv5t but doesn't fail on armv6t2 or armv7-a > because > > peephole doesn't trigger there (because there is a different epilogue > > sequence). It looks like a latent problem for other architecture or > CPUs. > > > > This patch adds this condition to the peephole optimizer. > > > > No regression on qemu for arm-none-eabi and fixes the test reported > in the > > PR. I couldn't minimize the test sufficiently to include it in the > > testsuite. > > > > Ok for trunk? > > > > Thanks, > > Greta > > > > gcc/ > > > > 2013-04-18 Greta Yorsh > > > > PR target/56797 > > * config/arm/arm.c (load_multiple_sequence): Require SP > > as base register for loads if SP is in the register list. > > > > OK. > > R. diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index d00849c..60fef78 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -10347,6 +10347,13 @@ load_multiple_sequence (rtx *operands, int nops, int *regs, int *saved_order, || (i != nops - 1 && unsorted_regs[i] == base_reg)) return 0; + /* Don't allow SP to be loaded unless it is also the base + register. It guarantees that SP is reset correctly when + an LDM instruction is interrupted. Otherwise, we might + end up with a corrupt stack. */ + if (unsorted_regs[i] == SP_REGNUM && base_reg != SP_REGNUM) + return 0; + unsorted_offsets[i] = INTVAL (offset); if (i == 0 || unsorted_offsets[i] < unsorted_offsets[order[0]]) order[0] = i;