From patchwork Mon Apr 22 23:10:33 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Helgaas X-Patchwork-Id: 238677 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id B9FEC2C014B for ; Tue, 23 Apr 2013 09:10:36 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753354Ab3DVXKg (ORCPT ); Mon, 22 Apr 2013 19:10:36 -0400 Received: from mail-ia0-f176.google.com ([209.85.210.176]:36797 "EHLO mail-ia0-f176.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753039Ab3DVXKf (ORCPT ); Mon, 22 Apr 2013 19:10:35 -0400 Received: by mail-ia0-f176.google.com with SMTP id i9so9599iad.21 for ; Mon, 22 Apr 2013 16:10:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:subject:to:from:cc:date:message-id:in-reply-to :references:user-agent:mime-version:content-type :content-transfer-encoding; bh=kI7u8NjyYmTcd9j7B7dkjEGquhfMJVudEsHm8TOHC1g=; b=jOwcSzfJ2oatLyoDVOHcUW0tZJDM8oY3ez2A7VsZj092o/sG/BP3yctNfF6xaHjkDQ A6icuzxcTLbwUp3BQG1YKF5mHnZd69OepkWeh/zTm1WxTzuJnhTAXg6smHDslNuhfRQQ 5Gb983EikiiuTIMmfwY5/7Mh0CWW80aS/ie6AK2x7wpNkCxn++4js/DVVbLyP0yGukLo EUVcxUkcXn0vnAsJXvJvLeRtiuw/I5TEowTm/UxWAejz72+BWyT1jfgyHKopHkTyfQ31 V7D0P3KqqQ2MIO3E91ewYPuQaRPPNi9yNGGpwGepm5nsjckuSFdtWiOGtDBzZxzyaLE4 z7jQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:subject:to:from:cc:date:message-id:in-reply-to :references:user-agent:mime-version:content-type :content-transfer-encoding:x-gm-message-state; bh=kI7u8NjyYmTcd9j7B7dkjEGquhfMJVudEsHm8TOHC1g=; b=IC9+ea0NSn5FeiN+TenAtno8u+nMR4eJCkHXyrq9wxyxyYqj4c1SZGAYtTjtPcbCPS esPEAmH/+xMEL+i81VC4uCFzTAlSoNCjDc7NlyTQjc2wVsL/aS0TCw/GefC9wYdpcIst 6cI1for/otqBNkWmqd5NiouNIusPJFEZzQ7HcowG865WnvjC5czyob7vRLRkebhRfvCY MqMiaZrF2Vg9/kETBKwd97QafRcdqHmYQFc8raaNF/Fn0O3gOX588CcMoAIqXhxJ++Wm 3+wtMOMFK58ND7sy3rMOD0Bpzi2gDhg+RpuK2/8aP/Hq+Uh82PcLsS3z73TdIhZ9Bq25 2aUQ== X-Received: by 10.50.32.69 with SMTP id g5mr4916933igi.104.1366672234902; Mon, 22 Apr 2013 16:10:34 -0700 (PDT) Received: from localhost ([172.29.120.215]) by mx.google.com with ESMTPS id b3sm12195742igd.5.2013.04.22.16.10.34 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 22 Apr 2013 16:10:34 -0700 (PDT) Subject: [PATCH v4 03/22] PCI: Cache MSI/MSI-X capability offsets in struct pci_dev To: linux-pci@vger.kernel.org From: Bjorn Helgaas Cc: Gavin Shan Date: Mon, 22 Apr 2013 17:10:33 -0600 Message-ID: <20130422231033.32621.34498.stgit@bhelgaas-glaptop> In-Reply-To: <20130422230012.32621.15224.stgit@bhelgaas-glaptop> References: <20130422230012.32621.15224.stgit@bhelgaas-glaptop> User-Agent: StGit/0.15 MIME-Version: 1.0 X-Gm-Message-State: ALoCoQmkUKhUJeIxv/LAolJhJNCe+nDYuNrzls83H2merULlXK8fv464O8DX3mknYtbMHaSN9oVifI7ahCjZPtP8FOu+MSBeDexDJecuVNVcHMjtv+4BLArNG1+MS/Lox4sG1bdxLXcx3OCwsDsgg4bd/hq61IPZFLtBZmmIrn5ekCuwK4kH/S3UR8rpRFlLFi+claGvrNU1C7IPhy8QixvfRniRsz9kYnKhlFfOuBDsVPNCOHEBvp4= Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Gavin Shan The patch caches the MSI and MSI-X capability offset in PCI device (struct pci_dev) so that we needn't read it from the config space upon enabling or disabling MSI or MSI-X interrupts. [bhelgaas: moved pm_cap size change to separate patch] Signed-off-by: Gavin Shan Signed-off-by: Bjorn Helgaas --- drivers/pci/msi.c | 42 +++++++++++++++++++----------------------- include/linux/pci.h | 2 ++ 2 files changed, 21 insertions(+), 23 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c index 00cc78c..99befbd 100644 --- a/drivers/pci/msi.c +++ b/drivers/pci/msi.c @@ -111,32 +111,26 @@ void default_restore_msi_irqs(struct pci_dev *dev, int irq) } #endif -static void msi_set_enable(struct pci_dev *dev, int pos, int enable) +static void msi_set_enable(struct pci_dev *dev, int enable) { u16 control; - BUG_ON(!pos); - - pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); + pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); control &= ~PCI_MSI_FLAGS_ENABLE; if (enable) control |= PCI_MSI_FLAGS_ENABLE; - pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); + pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); } static void msix_set_enable(struct pci_dev *dev, int enable) { - int pos; u16 control; - pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); - if (pos) { - pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); - control &= ~PCI_MSIX_FLAGS_ENABLE; - if (enable) - control |= PCI_MSIX_FLAGS_ENABLE; - pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); - } + pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); + control &= ~PCI_MSIX_FLAGS_ENABLE; + if (enable) + control |= PCI_MSIX_FLAGS_ENABLE; + pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); } static inline __attribute_const__ u32 msi_mask(unsigned x) @@ -402,7 +396,7 @@ static void __pci_restore_msi_state(struct pci_dev *dev) pos = entry->msi_attrib.pos; pci_intx_for_msi(dev, 0); - msi_set_enable(dev, pos, 0); + msi_set_enable(dev, 0); arch_restore_msi_irqs(dev, dev->irq); pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); @@ -557,7 +551,7 @@ static int msi_capability_init(struct pci_dev *dev, int nvec) unsigned mask; pos = pci_find_capability(dev, PCI_CAP_ID_MSI); - msi_set_enable(dev, pos, 0); /* Disable MSI during set up */ + msi_set_enable(dev, 0); /* Disable MSI during set up */ pci_read_config_word(dev, msi_control_reg(pos), &control); /* MSI Entry Initialization */ @@ -598,7 +592,7 @@ static int msi_capability_init(struct pci_dev *dev, int nvec) /* Set MSI enabled bits */ pci_intx_for_msi(dev, 0); - msi_set_enable(dev, pos, 1); + msi_set_enable(dev, 1); dev->msi_enabled = 1; dev->irq = entry->irq; @@ -885,7 +879,7 @@ void pci_msi_shutdown(struct pci_dev *dev) desc = list_first_entry(&dev->msi_list, struct msi_desc, list); pos = desc->msi_attrib.pos; - msi_set_enable(dev, pos, 0); + msi_set_enable(dev, 0); pci_intx_for_msi(dev, 1); dev->msi_enabled = 0; @@ -1048,15 +1042,17 @@ EXPORT_SYMBOL(pci_msi_enabled); void pci_msi_init_pci_dev(struct pci_dev *dev) { - int pos; INIT_LIST_HEAD(&dev->msi_list); /* Disable the msi hardware to avoid screaming interrupts * during boot. This is the power on reset default so * usually this should be a noop. */ - pos = pci_find_capability(dev, PCI_CAP_ID_MSI); - if (pos) - msi_set_enable(dev, pos, 0); - msix_set_enable(dev, 0); + dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI); + if (dev->msi_cap) + msi_set_enable(dev, 0); + + dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX); + if (dev->msix_cap) + msix_set_enable(dev, 0); } diff --git a/include/linux/pci.h b/include/linux/pci.h index 9587d4d..b73c246 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -232,6 +232,8 @@ struct pci_dev { u8 revision; /* PCI revision, low byte of class word */ u8 hdr_type; /* PCI header type (`multi' flag masked out) */ u8 pcie_cap; /* PCI-E capability offset */ + u8 msi_cap; /* MSI capability offset */ + u8 msix_cap; /* MSI-X capability offset */ u8 pcie_mpss:3; /* PCI-E Max Payload Size Supported */ u8 rom_base_reg; /* which config register controls the ROM */ u8 pin; /* which interrupt pin this device uses */