From patchwork Mon Apr 22 18:20:38 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mugunthan V N X-Patchwork-Id: 238614 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id E08422C0178 for ; Tue, 23 Apr 2013 04:21:03 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754611Ab3DVSU6 (ORCPT ); Mon, 22 Apr 2013 14:20:58 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:35215 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754546Ab3DVSU5 (ORCPT ); Mon, 22 Apr 2013 14:20:57 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id r3MIKrUI011550; Mon, 22 Apr 2013 13:20:53 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id r3MIKrWS032068; Mon, 22 Apr 2013 13:20:53 -0500 Received: from dlelxv23.itg.ti.com (172.17.1.198) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.2.342.3; Mon, 22 Apr 2013 13:20:52 -0500 Received: from psplinux063.india.ti.com (dbdp20.itg.ti.com [172.24.170.38]) by dlelxv23.itg.ti.com (8.13.8/8.13.8) with ESMTP id r3MIKi2X024482; Mon, 22 Apr 2013 13:20:51 -0500 From: Mugunthan V N To: CC: , , , Mugunthan V N Subject: [net-next PATCH 3/3] ARM: dts: AM33XX: add phy fixup for evm and evmsk boards Date: Mon, 22 Apr 2013 23:50:38 +0530 Message-ID: <1366654838-26479-4-git-send-email-mugunthanvnm@ti.com> X-Mailer: git-send-email 1.8.1 In-Reply-To: <1366654838-26479-1-git-send-email-mugunthanvnm@ti.com> References: <1366654838-26479-1-git-send-email-mugunthanvnm@ti.com> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org As RGMII tx clock internal delay is not supported in AM335x, the same has to be enabled in phy. This patch adds support for enabling tx clock internal delay via phy debug registers Signed-off-by: Mugunthan V N --- arch/arm/boot/dts/am335x-evm.dts | 10 ++++++++++ arch/arm/boot/dts/am335x-evmsk.dts | 10 ++++++++++ 2 files changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index d649644..72805c5 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -244,3 +244,13 @@ &cpsw_emac1 { phy_id = <&davinci_mdio>, <1>; }; + +&davinci_mdio { + phy-fixup-registers = <&atheros_txclk_delay_fixup>; + + atheros_txclk_delay_fixup: atheros_txclk_delay_fixup { + phy-id = <0x4dd074>; + phy-mask = <0xfffffffe>; + fixup-registers = <0x1d 0x5 0x1e 0x100>; + }; +}; diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index f297b85..f398cb3 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -256,3 +256,13 @@ &cpsw_emac1 { phy_id = <&davinci_mdio>, <1>; }; + +&davinci_mdio { + phy-fixup-registers = <&atheros_txclk_delay_fixup>; + + atheros_txclk_delay_fixup: atheros_txclk_delay_fixup { + phy-id = <0x4dd074>; + phy-mask = <0xfffffffe>; + fixup-registers = <0x1d 0x5 0x1e 0x100>; + }; +};