From patchwork Mon Apr 22 11:16:05 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dirk Eibach X-Patchwork-Id: 238455 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 4DF4C2C0121 for ; Mon, 22 Apr 2013 21:17:14 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D88CD4A33B; Mon, 22 Apr 2013 13:17:12 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id MJJc-0ovqr2K; Mon, 22 Apr 2013 13:17:12 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CB6364A33F; Mon, 22 Apr 2013 13:17:04 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id EF85F4A297 for ; Mon, 22 Apr 2013 13:16:57 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id o2hQcIV5YZLZ for ; Mon, 22 Apr 2013 13:16:56 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from sputnik.urmx.de (sputnik.urmx.de [88.198.51.18]) by theia.denx.de (Postfix) with ESMTP id 76CD94A29A for ; Mon, 22 Apr 2013 13:16:42 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by sputnik.urmx.de (Postfix) with ESMTP id 3686260222D5 for ; Mon, 22 Apr 2013 13:16:42 +0200 (CEST) X-Virus-Scanned: amavisd-new at urmx.de Received: from sputnik.urmx.de ([127.0.0.1]) by localhost (sputnik.urmx.de [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id MoT9wJyCQlDE for ; Mon, 22 Apr 2013 13:16:40 +0200 (CEST) Received: from utm1.gdsys.de (unknown [195.243.218.178]) by mforward1.urmx.de (Postfix) with ESMTPS id B83F360222D9 for ; Mon, 22 Apr 2013 13:16:40 +0200 (CEST) Received: from [172.16.100.239] (port=55403 helo=smgw1.gd.local) by utm1.gdsys.de with esmtp (Exim 4.76) (envelope-from ) id 1UUEjd-0000mk-3A for u-boot@lists.denx.de; Mon, 22 Apr 2013 13:16:37 +0200 Received: from smgw1.gd.local (localhost [127.0.0.1]) by smgw1.gd.local (Postfix) with ESMTP id E3D351A30FB for ; Mon, 22 Apr 2013 13:16:37 +0200 (CEST) From: Dirk Eibach To: u-boot@lists.denx.de, Stefan Roese Date: Mon, 22 Apr 2013 13:16:05 +0200 Message-Id: <1366629372-32022-5-git-send-email-eibach@gdsys.de> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1366629372-32022-1-git-send-email-eibach@gdsys.de> References: <1366629372-32022-1-git-send-email-eibach@gdsys.de> X-SafeGuard_MailGateway: Version: 5.80.2.12968 SGMG_SOPHOS Date: 20130422111637Z Subject: [U-Boot] [PATCH 04/11] powerpc/ppc4xx: Add bitbang i2c interface for gdsys boards X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de This adds an i2c bitbang interface that can coexist with processor i2c. Signed-off-by: Dirk Eibach --- board/gdsys/common/Makefile | 2 +- board/gdsys/common/bb_i2c.c | 304 +++++++++++++++++++++++++++++++++++++++++++ board/gdsys/common/bb_i2c.h | 76 +++++++++++ 3 files changed, 381 insertions(+), 1 deletion(-) create mode 100644 board/gdsys/common/bb_i2c.c create mode 100644 board/gdsys/common/bb_i2c.h diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile index aa15c15..b217d97 100644 --- a/board/gdsys/common/Makefile +++ b/board/gdsys/common/Makefile @@ -31,7 +31,7 @@ LIB = $(obj)lib$(VENDOR).o COBJS-$(CONFIG_IO) += miiphybb.o COBJS-$(CONFIG_IO64) += miiphybb.o -COBJS-$(CONFIG_IOCON) += osd.o mclink.o cmd_fpga.o +COBJS-$(CONFIG_IOCON) += osd.o mclink.o cmd_fpga.o bb_i2c.o COBJS-$(CONFIG_DLVISION_10G) += osd.o COBJS := $(COBJS-y) diff --git a/board/gdsys/common/bb_i2c.c b/board/gdsys/common/bb_i2c.c new file mode 100644 index 0000000..a816514 --- /dev/null +++ b/board/gdsys/common/bb_i2c.c @@ -0,0 +1,304 @@ +/* + * (C) Copyright 2012 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * based on soft_i2c.c + * (C) Copyright 2001, 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * This has been changed substantially by Gerald Van Baren, Custom IDEAS, + * vanbaren@cideas.com. It was heavily influenced by LiMon, written by + * Neil Russell. + */ + +#include + +/*----------------------------------------------------------------------- + * Definitions + */ + +#define RETRIES 0 + +#define BB_I2C_ACK 0 /* PD_SDA level to ack a byte */ +#define BB_I2C_NOACK 1 /* PD_SDA level to noack a byte */ + +/*----------------------------------------------------------------------- + * Local functions + */ +static void send_reset(unsigned int bus); +static void send_start(unsigned int bus); +static void send_stop(unsigned int bus); +static void send_ack(unsigned int bus, int ack); +static int write_byte(unsigned int bus, uchar byte); +static uchar read_byte(unsigned int bus, int ack); + +/*----------------------------------------------------------------------- + * Send a reset sequence consisting of 9 clocks with the data signal high + * to clock any confused device back into an idle state. Also send a + * at the end of the sequence for belts & suspenders. + */ +static void send_reset(unsigned int bus) +{ + BB_I2C_SOFT_DECLARATIONS(bus) /* intentional without ';' */ + int j; + + BB_I2C_SCL(bus, 1); + BB_I2C_SDA(bus, 1); + BB_I2C_TRISTATE(bus); + for (j = 0; j < 9; j++) { + BB_I2C_SCL(bus, 0); + BB_I2C_DELAY(bus); + BB_I2C_DELAY(bus); + BB_I2C_SCL(bus, 1); + BB_I2C_DELAY(bus); + BB_I2C_DELAY(bus); + } + send_stop(bus); + BB_I2C_TRISTATE(bus); +} + +/*----------------------------------------------------------------------- + * START: High -> Low on SDA while SCL is High + */ +static void send_start(unsigned int bus) +{ + BB_I2C_SOFT_DECLARATIONS(bus) /* intentional without ';' */ + + BB_I2C_DELAY(bus); + BB_I2C_SDA(bus, 1); + BB_I2C_ACTIVE(bus); + BB_I2C_DELAY(bus); + BB_I2C_SCL(bus, 1); + BB_I2C_DELAY(bus); + BB_I2C_SDA(bus, 0); + BB_I2C_DELAY(bus); +} + +/*----------------------------------------------------------------------- + * STOP: Low -> High on SDA while SCL is High + */ +static void send_stop(unsigned int bus) +{ + BB_I2C_SOFT_DECLARATIONS(bus) /* intentional without ';' */ + + BB_I2C_SCL(bus, 0); + BB_I2C_DELAY(bus); + BB_I2C_SDA(bus, 0); + BB_I2C_ACTIVE(bus); + BB_I2C_DELAY(bus); + BB_I2C_SCL(bus, 1); + BB_I2C_DELAY(bus); + BB_I2C_SDA(bus, 1); + BB_I2C_DELAY(bus); + BB_I2C_TRISTATE(bus); +} + +/*----------------------------------------------------------------------- + * ack should be BB_I2C_ACK or BB_I2C_NOACK + */ +static void send_ack(unsigned int bus, int ack) +{ + BB_I2C_SOFT_DECLARATIONS(bus) /* intentional without ';' */ + + BB_I2C_SCL(bus, 0); + BB_I2C_DELAY(bus); + BB_I2C_ACTIVE(bus); + BB_I2C_SDA(bus, ack); + BB_I2C_DELAY(bus); + BB_I2C_SCL(bus, 1); + BB_I2C_DELAY(bus); + BB_I2C_DELAY(bus); + BB_I2C_SCL(bus, 0); + BB_I2C_DELAY(bus); +} + +/*----------------------------------------------------------------------- + * Send 8 bits and look for an acknowledgement. + */ +static int write_byte(unsigned int bus, uchar data) +{ + BB_I2C_SOFT_DECLARATIONS(bus) /* intentional without ';' */ + int j; + int nack; + + BB_I2C_ACTIVE(bus); + for (j = 0; j < 8; j++) { + BB_I2C_SCL(bus, 0); + BB_I2C_DELAY(bus); + BB_I2C_SDA(bus, data & 0x80); + BB_I2C_DELAY(bus); + BB_I2C_SCL(bus, 1); + BB_I2C_DELAY(bus); + BB_I2C_DELAY(bus); + + data <<= 1; + } + + /* + * Look for an (negative logic) and return it. + */ + BB_I2C_SCL(bus, 0); + BB_I2C_DELAY(bus); + BB_I2C_SDA(bus, 1); + BB_I2C_TRISTATE(bus); + BB_I2C_DELAY(bus); + BB_I2C_SCL(bus, 1); + BB_I2C_DELAY(bus); + BB_I2C_DELAY(bus); + nack = BB_I2C_READ(bus); + BB_I2C_SCL(bus, 0); + BB_I2C_DELAY(bus); + BB_I2C_ACTIVE(bus); + + return nack; /* not a nack is an ack */ +} + +/*----------------------------------------------------------------------- + * if ack == BB_I2C_ACK, ACK the byte so can continue reading, else + * send BB_I2C_NOACK to end the read. + */ +static uchar read_byte(unsigned int bus, int ack) +{ + BB_I2C_SOFT_DECLARATIONS(bus) /* intentional without ';' */ + int data; + int j; + + /* + * Read 8 bits, MSB first. + */ + BB_I2C_TRISTATE(bus); + BB_I2C_SDA(bus, 1); + data = 0; + for (j = 0; j < 8; j++) { + BB_I2C_SCL(bus, 0); + BB_I2C_DELAY(bus); + BB_I2C_SCL(bus, 1); + BB_I2C_DELAY(bus); + data <<= 1; + data |= BB_I2C_READ(bus); + BB_I2C_DELAY(bus); + } + send_ack(bus, ack); + + return data; +} + +/*=====================================================================*/ +/* Public Functions */ +/*=====================================================================*/ + +/*----------------------------------------------------------------------- + * Initialization + */ +void bb_i2c_init(unsigned int bus, int speed, int slaveaddr) +{ + send_reset(bus); +} + +/*----------------------------------------------------------------------- + * Probe to see if a chip is present. Also good for checking for the + * completion of EEPROM writes since the chip stops responding until + * the write completes (typically 10mSec). + */ +int bb_i2c_probe(unsigned int bus, uchar addr) +{ + int rc; + + /* + * perform 1 byte write transaction with just address byte + * (fake write) + */ + send_start(bus); + rc = write_byte(bus, (addr << 1) | 0); + send_stop(bus); + + return rc ? 1 : 0; +} + +/*----------------------------------------------------------------------- + * Read bytes + */ +int bb_i2c_read(unsigned int bus, uchar chip, uint addr, int alen, + uchar *buffer, int len) +{ + int shift; + + /* + * Do the addressing portion of a write cycle to set the + * chip's address pointer. If the address length is zero, + * don't do the normal write cycle to set the address pointer, + * there is no address pointer in this chip. + */ + send_start(bus); + if (alen > 0) { + if (write_byte(bus, chip << 1)) { /* write cycle */ + send_stop(bus); + return 1; + } + shift = (alen-1) * 8; + while (alen-- > 0) { + if (write_byte(bus, addr >> shift)) + return 1; + shift -= 8; + } + + send_stop(bus); + send_start(bus); + } + /* + * Send the chip address again, this time for a read cycle. + * Then read the data. On the last byte, we do a NACK instead + * of an ACK(len == 0) to terminate the read. + */ + write_byte(bus, (chip << 1) | 1); /* read cycle */ + while (len-- > 0) + *buffer++ = read_byte(bus, len == 0); + send_stop(bus); + return 0; +} + +/*----------------------------------------------------------------------- + * Write bytes + */ +int bb_i2c_write(unsigned int bus, uchar chip, uint addr, int alen, + uchar *buffer, int len) +{ + int shift, failures = 0; + + send_start(bus); + if (write_byte(bus, chip << 1)) { /* write cycle */ + send_stop(bus); + return 1; + } + shift = (alen-1) * 8; + while (alen-- > 0) { + if (write_byte(bus, addr >> shift)) + return 1; + shift -= 8; + } + + while (len-- > 0) { + if (write_byte(bus, *buffer++)) + failures++; + } + send_stop(bus); + return failures; +} diff --git a/board/gdsys/common/bb_i2c.h b/board/gdsys/common/bb_i2c.h new file mode 100644 index 0000000..34f4c0f --- /dev/null +++ b/board/gdsys/common/bb_i2c.h @@ -0,0 +1,76 @@ +/* + * (C) Copyright 2012 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * based on i2c.h + * (C) Copyright 2001 + * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * The original I2C interface was + * (C) 2000 by Paolo Scaffardi (arsenio@tin.it) + * AIRVENT SAM s.p.a - RIMINI(ITALY) + * but has been changed substantially. + */ + +#ifndef _BB_I2C_H_ +#define _BB_I2C_H_ + +/* + * Probe the given I2C chip address. Returns 0 if a chip responded, + * not 0 on failure. + */ +int bb_i2c_probe(unsigned int bus, uchar chip); + +/* + * Read/Write interface: + * chip: I2C chip address, range 0..127 + * addr: Memory (register) address within the chip + * alen: Number of bytes to use for addr (typically 1, 2 for larger + * memories, 0 for register type devices with only one + * register) + * buffer: Where to read/write the data + * len: How many bytes to read/write + * + * Returns: 0 on success, not 0 on failure + */ +int bb_i2c_read(unsigned int bus, uchar chip, uint addr, int alen, + uchar *buffer, int len); +int bb_i2c_write(unsigned int bus, uchar chip, uint addr, int alen, + uchar *buffer, int len); + +/* + * Utility routines to read/write registers. + */ +static inline u8 bb_i2c_reg_read(unsigned int bus, u8 addr, u8 reg) +{ + u8 buf; + + bb_i2c_read(bus, addr, reg, 1, &buf, 1); + + return buf; +} + +static inline void bb_i2c_reg_write(unsigned int bus, u8 addr, u8 reg, u8 val) +{ + bb_i2c_write(bus, addr, reg, 1, &val, 1); +} + +#endif /* _BB_I2C_H_ */