From patchwork Mon Apr 22 05:15:13 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Crosthwaite X-Patchwork-Id: 238325 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 701282C00F7 for ; Mon, 22 Apr 2013 15:17:38 +1000 (EST) Received: from localhost ([::1]:58154 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UU98C-0002ri-J6 for incoming@patchwork.ozlabs.org; Mon, 22 Apr 2013 01:17:36 -0400 Received: from eggs.gnu.org ([208.118.235.92]:59113) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UU97i-0002fI-4n for qemu-devel@nongnu.org; Mon, 22 Apr 2013 01:17:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UU97h-0004SX-4D for qemu-devel@nongnu.org; Mon, 22 Apr 2013 01:17:06 -0400 Received: from mail-pa0-f47.google.com ([209.85.220.47]:51271) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UU97g-0004ST-V0 for qemu-devel@nongnu.org; Mon, 22 Apr 2013 01:17:05 -0400 Received: by mail-pa0-f47.google.com with SMTP id bj1so1424485pad.20 for ; Sun, 21 Apr 2013 22:17:04 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references:x-gm-message-state; bh=vNCufYln3R/IqBUw/pCB0yNc7A9vVqS+Wzxi1JAxwT4=; b=aklgORSaOJ9KLgSal/PwGcAn4JwaAl0kCT8vs1CoT4HHxym8MnH64U9O4dt95Et1VY qLnd0RuOXomh5ydORvO3+2LSGGeru5HMhAUFWQstefjM6q/NAXVQT/RFDqwsUkM9GroG 08r2wwPO9xYSVqFGmYsW2GsfcykPu7KH2J8XlOs7NCBV2ug6boTzLIT14foczdnc6cTX 1hJrFGwAEEqHzf3Ep4AMk/DMoxS+gIQhMeebAxmzZkd/sQgzE8TOfUvIj0jWuQHQyS80 M82dtH807lHE1GqfLVH8z09c9KXCxAskAWb8g2t2VEBkZCs9XxJ3C8W3NASSz1ei1lcA n72g== X-Received: by 10.68.94.227 with SMTP id df3mr30280433pbb.182.1366607824336; Sun, 21 Apr 2013 22:17:04 -0700 (PDT) Received: from localhost ([149.199.62.254]) by mx.google.com with ESMTPS id ef4sm23519072pbd.38.2013.04.21.22.17.02 (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Sun, 21 Apr 2013 22:17:03 -0700 (PDT) From: peter.crosthwaite@xilinx.com To: qemu-devel@nongnu.org Date: Mon, 22 Apr 2013 15:15:13 +1000 Message-Id: <6abe6d94a7290572cf0eea41fe9c7f04576b14b0.1366606958.git.peter.crosthwaite@xilinx.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: References: X-Gm-Message-State: ALoCoQkdwo36kbZlT5HlQLT0cYyYMk4H/RfM7RwvPyPkja6bo3BgJD9z1gbrTGT1jTtF5OEP9iDi X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 209.85.220.47 Cc: peter.maydell@linaro.org, edgar.iglesias@gmail.com Subject: [Qemu-devel] [PATCH for-1.5 v3 06/15] xilinx_spips: Trash LQ page cache on mode change X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Peter Crosthwaite Invalidate the LQSPI cached page when transitioning into LQSPI mode. Otherwise there is a possibility that the controller will return stale data to the guest when transitioning back to LQ_MODE after a page program. Signed-off-by: Peter Crosthwaite Reviewed-by: Peter Maydell --- changed from v2: Removed extraneous break after goto (PMM review) changed from v1: Re-implemented using separate SPI/QSPI write handlers. hw/ssi/xilinx_spips.c | 25 ++++++++++++++++++++++++- 1 files changed, 24 insertions(+), 1 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index e351cb2..a7ba702 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -165,6 +165,8 @@ typedef struct { typedef struct XilinxSPIPSClass { SysBusDeviceClass parent_class; + const MemoryRegionOps *reg_ops; + uint32_t rx_fifo_size; uint32_t tx_fifo_size; } XilinxSPIPSClass; @@ -462,6 +464,25 @@ static const MemoryRegionOps spips_ops = { .endianness = DEVICE_LITTLE_ENDIAN, }; +static void xilinx_qspips_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size) +{ + XilinxQSPIPS *q = XILINX_QSPIPS(opaque); + + xilinx_spips_write(opaque, addr, value, size); + addr >>= 2; + + if (addr == R_LQSPI_CFG) { + q->lqspi_cached_addr = ~0ULL; + } +} + +static const MemoryRegionOps qspips_ops = { + .read = xilinx_spips_read, + .write = xilinx_qspips_write, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + #define LQSPI_CACHE_SIZE 1024 static uint64_t @@ -565,7 +586,7 @@ static void xilinx_spips_realize(DeviceState *dev, Error **errp) sysbus_init_irq(sbd, &s->cs_lines[i]); } - memory_region_init_io(&s->iomem, &spips_ops, s, "spi", R_MAX*4); + memory_region_init_io(&s->iomem, xsc->reg_ops, s, "spi", R_MAX*4); sysbus_init_mmio(sbd, &s->iomem); s->irqline = -1; @@ -629,6 +650,7 @@ static void xilinx_qspips_class_init(ObjectClass *klass, void * data) XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass); dc->realize = xilinx_qspips_realize; + xsc->reg_ops = &qspips_ops; xsc->rx_fifo_size = RXFF_A_Q; xsc->tx_fifo_size = TXFF_A_Q; } @@ -643,6 +665,7 @@ static void xilinx_spips_class_init(ObjectClass *klass, void *data) dc->props = xilinx_spips_properties; dc->vmsd = &vmstate_xilinx_spips; + xsc->reg_ops = &spips_ops; xsc->rx_fifo_size = RXFF_A; xsc->tx_fifo_size = TXFF_A; }