From patchwork Mon Apr 22 05:13:16 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Crosthwaite X-Patchwork-Id: 238322 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id E23912C00D8 for ; Mon, 22 Apr 2013 15:15:37 +1000 (EST) Received: from localhost ([::1]:53624 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UU96G-0000Cj-2s for incoming@patchwork.ozlabs.org; Mon, 22 Apr 2013 01:15:36 -0400 Received: from eggs.gnu.org ([208.118.235.92]:58760) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UU95p-0008Qk-OA for qemu-devel@nongnu.org; Mon, 22 Apr 2013 01:15:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UU95o-0003se-RB for qemu-devel@nongnu.org; Mon, 22 Apr 2013 01:15:09 -0400 Received: from mail-da0-x234.google.com ([2607:f8b0:400e:c00::234]:56558) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UU95o-0003sZ-DV for qemu-devel@nongnu.org; Mon, 22 Apr 2013 01:15:08 -0400 Received: by mail-da0-f52.google.com with SMTP id j17so598956dan.25 for ; Sun, 21 Apr 2013 22:15:07 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references:x-gm-message-state; bh=nLzCwBt3rvbBJ700M0kyXiiKbXtKXKrT5GZmT9HFp/4=; b=BYKZQwkIPlkYki4Y3zUvJ1KFVvlSTZa0aGqlADmrJeK+bKPnd9VtelNbNm0YRDvAeh yTFImTi8kvdq7R6TXn2zxK5gYEWnQuRhxgk70+x0XyDKrIuN+kDVLhGE4psqycDyRas/ EU5xlh7vCFxg3RDbxu870CjPgTYdIWRd59BMFUgM4RoiaZ6icTBNTJFl0+mcIomVWxwP 8f58TTz9c2SDPlyP+WxU7xzsADmt0jfhtfAeCrMqrGz+Tg/YVVjQUFydn6quo8higFGP qYaKMFGLhZqJFDxUaP2/83gngKDYKe6kxLlap8fzKDqRz2f0mPHs8lVZEeP3cRy3k9Vt DuyQ== X-Received: by 10.66.121.169 with SMTP id ll9mr10655951pab.178.1366607707757; Sun, 21 Apr 2013 22:15:07 -0700 (PDT) Received: from localhost ([149.199.62.254]) by mx.google.com with ESMTPS id o7sm23495702pbs.45.2013.04.21.22.15.05 (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Sun, 21 Apr 2013 22:15:06 -0700 (PDT) From: peter.crosthwaite@xilinx.com To: qemu-devel@nongnu.org Date: Mon, 22 Apr 2013 15:13:16 +1000 Message-Id: <0d00103f581ec4bfdd3d127985177c59a262e2db.1366606958.git.peter.crosthwaite@xilinx.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: References: X-Gm-Message-State: ALoCoQn+rDLHz5PPsHElF+Q6cQy3jlBi7LyknOCQPnwaPelslMT2p9vcbJibwKe1wYfhxUC8sX2t X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c00::234 Cc: peter.maydell@linaro.org, edgar.iglesias@gmail.com Subject: [Qemu-devel] [PATCH for-1.5 v3 03/15] xilinx_spips: Inhibit interrupts in LQSPI mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Peter Crosthwaite The real hardware does not produce interrupts in LQSPI mode. Inhibit generation of interrupts when the LQ_MODE bit is set. Signed-off-by: Peter Crosthwaite Reviewed-by: Peter Maydell --- hw/ssi/xilinx_spips.c | 7 ++++++- 1 files changed, 6 insertions(+), 1 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 261d948..a8691d5 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -204,6 +204,9 @@ static void xilinx_spips_update_cs_lines(XilinxSPIPS *s) static void xilinx_spips_update_ixr(XilinxSPIPS *s) { + if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE) { + return; + } /* These are set/cleared as they occur */ s->regs[R_INTR_STATUS] &= (IXR_TX_FIFO_UNDERFLOW | IXR_RX_FIFO_OVERFLOW | IXR_TX_FIFO_MODE_FAIL); @@ -256,7 +259,9 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) for (i = 0; i < num_effective_busses(s); ++i) { if (!i || s->snoop_state == SNOOP_STRIPING) { if (fifo8_is_empty(&s->tx_fifo)) { - s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW; + if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) { + s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW; + } xilinx_spips_update_ixr(s); return; } else {