From patchwork Mon Apr 22 03:33:30 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: liguang X-Patchwork-Id: 238299 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id B84FB2C010C for ; Mon, 22 Apr 2013 13:39:17 +1000 (EST) Received: from localhost ([::1]:57900 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UU7b1-0005Ef-V0 for incoming@patchwork.ozlabs.org; Sun, 21 Apr 2013 23:39:15 -0400 Received: from eggs.gnu.org ([208.118.235.92]:39497) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UU7XX-0000xs-Ch for qemu-devel@nongnu.org; Sun, 21 Apr 2013 23:35:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UU7XS-0006YZ-Vz for qemu-devel@nongnu.org; Sun, 21 Apr 2013 23:35:39 -0400 Received: from [222.73.24.84] (port=63377 helo=song.cn.fujitsu.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UU7XS-0006VN-32 for qemu-devel@nongnu.org; Sun, 21 Apr 2013 23:35:34 -0400 X-IronPort-AV: E=Sophos;i="4.87,523,1363104000"; d="scan'208";a="7109046" Received: from unknown (HELO tang.cn.fujitsu.com) ([10.167.250.3]) by song.cn.fujitsu.com with ESMTP; 22 Apr 2013 11:32:51 +0800 Received: from fnstmail02.fnst.cn.fujitsu.com (tang.cn.fujitsu.com [127.0.0.1]) by tang.cn.fujitsu.com (8.14.3/8.13.1) with ESMTP id r3M3ZUcc026191; Mon, 22 Apr 2013 11:35:32 +0800 Received: from liguang.fnst.cn.fujitsu.com ([10.167.233.147]) by fnstmail02.fnst.cn.fujitsu.com (Lotus Domino Release 8.5.3) with ESMTP id 2013042211340165-715396 ; Mon, 22 Apr 2013 11:34:01 +0800 From: liguang To: qemu-devel@nongnu.org Date: Mon, 22 Apr 2013 11:33:30 +0800 Message-Id: <1366601610-15429-13-git-send-email-lig.fnst@cn.fujitsu.com> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1366601610-15429-1-git-send-email-lig.fnst@cn.fujitsu.com> References: <1366601610-15429-1-git-send-email-lig.fnst@cn.fujitsu.com> X-MIMETrack: Itemize by SMTP Server on mailserver/fnst(Release 8.5.3|September 15, 2011) at 2013/04/22 11:34:01, Serialize by Router on mailserver/fnst(Release 8.5.3|September 15, 2011) at 2013/04/22 11:34:02, Serialize complete at 2013/04/22 11:34:02 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 222.73.24.84 Cc: peter.maydell@linaro.org, ehabkost@redhat.com, blauwirbel@gmail.com, avi@redhat.com, imammedo@redhat.com, pbonzini@redhat.com, afaerber@suse.de, liguang , rth@twiddle.net Subject: [Qemu-devel] [PATCH 12/12] target-i386: fix over 80 chars warnings X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: liguang --- target-i386/misc_helper.c | 39 ++++++++++++++++++++++++++------------- target-i386/seg_helper.c | 16 +++++++++------- target-i386/svm_helper.c | 6 ++++-- 3 files changed, 39 insertions(+), 22 deletions(-) diff --git a/target-i386/misc_helper.c b/target-i386/misc_helper.c index 01d53fc..2dadbc2 100644 --- a/target-i386/misc_helper.c +++ b/target-i386/misc_helper.c @@ -122,7 +122,8 @@ void helper_cpuid(CPUX86State *env) cpu_svm_check_intercept_param(env, SVM_EXIT_CPUID, 0); - cpu_x86_cpuid(env, (uint32_t)env->regs[R_EAX], (uint32_t)env->regs[R_ECX], &eax, &ebx, &ecx, &edx); + cpu_x86_cpuid(env, (uint32_t)env->regs[R_EAX], (uint32_t)env->regs[R_ECX], + &eax, &ebx, &ecx, &edx); env->regs[R_EAX] = eax; env->regs[R_EBX] = ebx; env->regs[R_ECX] = ecx; @@ -271,7 +272,8 @@ void helper_wrmsr(CPUX86State *env) cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 1); - val = ((uint32_t)env->regs[R_EAX]) | ((uint64_t)((uint32_t)env->regs[R_EDX]) << 32); + val = ((uint32_t)env->regs[R_EAX]) | + ((uint64_t)((uint32_t)env->regs[R_EDX]) << 32); switch ((uint32_t)env->regs[R_ECX]) { case MSR_IA32_SYSENTER_CS: @@ -350,7 +352,8 @@ void helper_wrmsr(CPUX86State *env) case MSR_MTRRphysBase(5): case MSR_MTRRphysBase(6): case MSR_MTRRphysBase(7): - env->mtrr_var[((uint32_t)env->regs[R_ECX] - MSR_MTRRphysBase(0)) / 2].base = val; + env->mtrr_var[((uint32_t)env->regs[R_ECX] - + MSR_MTRRphysBase(0)) / 2].base = val; break; case MSR_MTRRphysMask(0): case MSR_MTRRphysMask(1): @@ -360,14 +363,17 @@ void helper_wrmsr(CPUX86State *env) case MSR_MTRRphysMask(5): case MSR_MTRRphysMask(6): case MSR_MTRRphysMask(7): - env->mtrr_var[((uint32_t)env->regs[R_ECX] - MSR_MTRRphysMask(0)) / 2].mask = val; + env->mtrr_var[((uint32_t)env->regs[R_ECX] - + MSR_MTRRphysMask(0)) / 2].mask = val; break; case MSR_MTRRfix64K_00000: - env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - MSR_MTRRfix64K_00000] = val; + env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - + MSR_MTRRfix64K_00000] = val; break; case MSR_MTRRfix16K_80000: case MSR_MTRRfix16K_A0000: - env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - MSR_MTRRfix16K_80000 + 1] = val; + env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - + MSR_MTRRfix16K_80000 + 1] = val; break; case MSR_MTRRfix4K_C0000: case MSR_MTRRfix4K_C8000: @@ -377,7 +383,8 @@ void helper_wrmsr(CPUX86State *env) case MSR_MTRRfix4K_E8000: case MSR_MTRRfix4K_F0000: case MSR_MTRRfix4K_F8000: - env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - MSR_MTRRfix4K_C0000 + 3] = val; + env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - + MSR_MTRRfix4K_C0000 + 3] = val; break; case MSR_MTRRdefType: env->mtrr_deftype = val; @@ -399,7 +406,8 @@ void helper_wrmsr(CPUX86State *env) break; default: if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL - && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL + (4 * env->mcg_cap & 0xff)) { + && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL + + (4 * env->mcg_cap & 0xff)) { uint32_t offset = (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL; if ((offset & 0x3) != 0 || (val == 0 || val == ~(uint64_t)0)) { @@ -480,7 +488,8 @@ void helper_rdmsr(CPUX86State *env) case MSR_MTRRphysBase(5): case MSR_MTRRphysBase(6): case MSR_MTRRphysBase(7): - val = env->mtrr_var[((uint32_t)env->regs[R_ECX] - MSR_MTRRphysBase(0)) / 2].base; + val = env->mtrr_var[((uint32_t)env->regs[R_ECX] - + MSR_MTRRphysBase(0)) / 2].base; break; case MSR_MTRRphysMask(0): case MSR_MTRRphysMask(1): @@ -490,14 +499,16 @@ void helper_rdmsr(CPUX86State *env) case MSR_MTRRphysMask(5): case MSR_MTRRphysMask(6): case MSR_MTRRphysMask(7): - val = env->mtrr_var[((uint32_t)env->regs[R_ECX] - MSR_MTRRphysMask(0)) / 2].mask; + val = env->mtrr_var[((uint32_t)env->regs[R_ECX] - + MSR_MTRRphysMask(0)) / 2].mask; break; case MSR_MTRRfix64K_00000: val = env->mtrr_fixed[0]; break; case MSR_MTRRfix16K_80000: case MSR_MTRRfix16K_A0000: - val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - MSR_MTRRfix16K_80000 + 1]; + val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - + MSR_MTRRfix16K_80000 + 1]; break; case MSR_MTRRfix4K_C0000: case MSR_MTRRfix4K_C8000: @@ -507,7 +518,8 @@ void helper_rdmsr(CPUX86State *env) case MSR_MTRRfix4K_E8000: case MSR_MTRRfix4K_F0000: case MSR_MTRRfix4K_F8000: - val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - MSR_MTRRfix4K_C0000 + 3]; + val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - + MSR_MTRRfix4K_C0000 + 3]; break; case MSR_MTRRdefType: val = env->mtrr_deftype; @@ -539,7 +551,8 @@ void helper_rdmsr(CPUX86State *env) break; default: if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL - && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL + (4 * env->mcg_cap & 0xff)) { + && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL + + (4 * env->mcg_cap & 0xff)) { uint32_t offset = (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL; val = env->mce_banks[offset]; break; diff --git a/target-i386/seg_helper.c b/target-i386/seg_helper.c index df26649..bb9912c 100644 --- a/target-i386/seg_helper.c +++ b/target-i386/seg_helper.c @@ -1811,9 +1811,9 @@ void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip, if (!(e2 & DESC_C_MASK) && dpl < cpl) { /* to inner privilege */ get_ss_esp_from_tss(env, &ss, &sp, dpl); - LOG_PCALL("new ss:esp=%04x:%08x param_count=%d env->regs[R_ESP]=" TARGET_FMT_lx - "\n", - ss, sp, param_count, env->regs[R_ESP]); + LOG_PCALL("new ss:esp=%04x:%08x param_count=%d env->regs[R_ESP]=" + TARGET_FMT_lx "\n", ss, sp, param_count, + env->regs[R_ESP]); if ((ss & 0xfffc) == 0) { raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc); } @@ -1847,16 +1847,18 @@ void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip, PUSHL(ssp, sp, sp_mask, env->segs[R_SS].selector); PUSHL(ssp, sp, sp_mask, env->regs[R_ESP]); for (i = param_count - 1; i >= 0; i--) { - val = cpu_ldl_kernel(env, old_ssp + ((env->regs[R_ESP] + i * 4) & - old_sp_mask)); + val = cpu_ldl_kernel(env, old_ssp + + ((env->regs[R_ESP] + i * 4) & + old_sp_mask)); PUSHL(ssp, sp, sp_mask, val); } } else { PUSHW(ssp, sp, sp_mask, env->segs[R_SS].selector); PUSHW(ssp, sp, sp_mask, env->regs[R_ESP]); for (i = param_count - 1; i >= 0; i--) { - val = cpu_lduw_kernel(env, old_ssp + ((env->regs[R_ESP] + i * 2) & - old_sp_mask)); + val = cpu_lduw_kernel(env, old_ssp + + ((env->regs[R_ESP] + i * 2) & + old_sp_mask)); PUSHW(ssp, sp, sp_mask, val); } } diff --git a/target-i386/svm_helper.c b/target-i386/svm_helper.c index e18fa35..4a7de42 100644 --- a/target-i386/svm_helper.c +++ b/target-i386/svm_helper.c @@ -658,8 +658,10 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1) R_DS); env->eip = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.rip)); - env->regs[R_ESP] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.rsp)); - env->regs[R_EAX] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.rax)); + env->regs[R_ESP] = ldq_phys(env->vm_hsave + + offsetof(struct vmcb, save.rsp)); + env->regs[R_EAX] = ldq_phys(env->vm_hsave + + offsetof(struct vmcb, save.rax)); env->dr[6] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.dr6)); env->dr[7] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.dr7));