Patchwork [v2,05/10] target-ppc: emulate prtyw and prtyd instructions

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Submitter Aurelien Jarno
Date April 20, 2013, 6:56 p.m.
Message ID <1366484182-29187-6-git-send-email-aurelien@aurel32.net>
Download mbox | patch
Permalink /patch/238176/
State New
Headers show

Comments

Aurelien Jarno - April 20, 2013, 6:56 p.m.
Needed for Power ISA version 2.05 compliance.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
 target-ppc/translate.c |   38 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)
Alexander Graf - April 26, 2013, 7:50 a.m.
On 20.04.2013, at 20:56, Aurelien Jarno wrote:

> Needed for Power ISA version 2.05 compliance.
> 
> Reviewed-by: Richard Henderson <rth@twiddle.net>
> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
> ---
> target-ppc/translate.c |   38 ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 38 insertions(+)
> 
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 6bee6db..977f9ef 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -1458,6 +1458,42 @@ static void gen_popcntd(DisasContext *ctx)
> }
> #endif
> 
> +/* prtyw: PowerPC 2.05 specification */
> +static void gen_prtyw(DisasContext *ctx)
> +{
> +    TCGv ra = cpu_gpr[rA(ctx->opcode)];
> +    TCGv rs = cpu_gpr[rS(ctx->opcode)];
> +    TCGv t0 = tcg_temp_new();
> +    tcg_gen_shri_tl(t0, rs, 16);
> +    tcg_gen_xor_tl(ra, rs, t0);
> +    tcg_gen_shri_tl(t0, ra, 8);
> +    tcg_gen_xor_tl(ra, ra, t0);
> +#if defined(TARGET_PPC64)
> +    tcg_gen_andi_tl(ra, ra, 0x100000001);

This will break on 32-bit host systems. Let me fix it to ULL for you :). In fact, any reason for the #ifdef here? We could just always pass 0x100000001ULL and have the target_ulong cast take the upper 32bit away, no?


Alex

> +#else
> +    tcg_gen_andi_tl(ra, ra, 1);
> +#endif
> +    tcg_temp_free(t0);
> +}
> +
> +#if defined(TARGET_PPC64)
> +/* prtyd: PowerPC 2.05 specification */
> +static void gen_prtyd(DisasContext *ctx)
> +{
> +    TCGv ra = cpu_gpr[rA(ctx->opcode)];
> +    TCGv rs = cpu_gpr[rS(ctx->opcode)];
> +    TCGv t0 = tcg_temp_new();
> +    tcg_gen_shri_tl(t0, rs, 32);
> +    tcg_gen_xor_tl(ra, rs, t0);
> +    tcg_gen_shri_tl(t0, ra, 16);
> +    tcg_gen_xor_tl(ra, ra, t0);
> +    tcg_gen_shri_tl(t0, ra, 8);
> +    tcg_gen_xor_tl(ra, ra, t0);
> +    tcg_gen_andi_tl(ra, ra, 1);
> +    tcg_temp_free(t0);
> +}
> +#endif
> +
> #if defined(TARGET_PPC64)
> /* extsw & extsw. */
> GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
> @@ -8489,9 +8525,11 @@ GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
> GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
> GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB),
> GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
> +GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
> #if defined(TARGET_PPC64)
> GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
> GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
> +GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
> #endif
> GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
> GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
> -- 
> 1.7.10.4
>
Aurelien Jarno - April 26, 2013, 9:38 a.m.
On Fri, Apr 26, 2013 at 09:50:31AM +0200, Alexander Graf wrote:
> 
> On 20.04.2013, at 20:56, Aurelien Jarno wrote:
> 
> > Needed for Power ISA version 2.05 compliance.
> > 
> > Reviewed-by: Richard Henderson <rth@twiddle.net>
> > Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
> > ---
> > target-ppc/translate.c |   38 ++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 38 insertions(+)
> > 
> > diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> > index 6bee6db..977f9ef 100644
> > --- a/target-ppc/translate.c
> > +++ b/target-ppc/translate.c
> > @@ -1458,6 +1458,42 @@ static void gen_popcntd(DisasContext *ctx)
> > }
> > #endif
> > 
> > +/* prtyw: PowerPC 2.05 specification */
> > +static void gen_prtyw(DisasContext *ctx)
> > +{
> > +    TCGv ra = cpu_gpr[rA(ctx->opcode)];
> > +    TCGv rs = cpu_gpr[rS(ctx->opcode)];
> > +    TCGv t0 = tcg_temp_new();
> > +    tcg_gen_shri_tl(t0, rs, 16);
> > +    tcg_gen_xor_tl(ra, rs, t0);
> > +    tcg_gen_shri_tl(t0, ra, 8);
> > +    tcg_gen_xor_tl(ra, ra, t0);
> > +#if defined(TARGET_PPC64)
> > +    tcg_gen_andi_tl(ra, ra, 0x100000001);
> 
> This will break on 32-bit host systems. Let me fix it to ULL for you :). In fact, any reason for the #ifdef here? We could just always pass 0x100000001ULL and have the target_ulong cast take the upper 32bit away, no?

Good catch. The #ifdef version matches the instruction definition in the
manual, but for QEMU I agree a version using a cast with target_ulong
looks better. Should I send a new patch?

Aurélien
Alexander Graf - April 26, 2013, 9:53 a.m.
On 26.04.2013, at 11:38, Aurelien Jarno wrote:

> On Fri, Apr 26, 2013 at 09:50:31AM +0200, Alexander Graf wrote:
>> 
>> On 20.04.2013, at 20:56, Aurelien Jarno wrote:
>> 
>>> Needed for Power ISA version 2.05 compliance.
>>> 
>>> Reviewed-by: Richard Henderson <rth@twiddle.net>
>>> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
>>> ---
>>> target-ppc/translate.c |   38 ++++++++++++++++++++++++++++++++++++++
>>> 1 file changed, 38 insertions(+)
>>> 
>>> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
>>> index 6bee6db..977f9ef 100644
>>> --- a/target-ppc/translate.c
>>> +++ b/target-ppc/translate.c
>>> @@ -1458,6 +1458,42 @@ static void gen_popcntd(DisasContext *ctx)
>>> }
>>> #endif
>>> 
>>> +/* prtyw: PowerPC 2.05 specification */
>>> +static void gen_prtyw(DisasContext *ctx)
>>> +{
>>> +    TCGv ra = cpu_gpr[rA(ctx->opcode)];
>>> +    TCGv rs = cpu_gpr[rS(ctx->opcode)];
>>> +    TCGv t0 = tcg_temp_new();
>>> +    tcg_gen_shri_tl(t0, rs, 16);
>>> +    tcg_gen_xor_tl(ra, rs, t0);
>>> +    tcg_gen_shri_tl(t0, ra, 8);
>>> +    tcg_gen_xor_tl(ra, ra, t0);
>>> +#if defined(TARGET_PPC64)
>>> +    tcg_gen_andi_tl(ra, ra, 0x100000001);
>> 
>> This will break on 32-bit host systems. Let me fix it to ULL for you :). In fact, any reason for the #ifdef here? We could just always pass 0x100000001ULL and have the target_ulong cast take the upper 32bit away, no?
> 
> Good catch. The #ifdef version matches the instruction definition in the
> manual, but for QEMU I agree a version using a cast with target_ulong
> looks better. Should I send a new patch?

I already fixed it up while applying the patch, thanks :)


Alex
Aurelien Jarno - April 26, 2013, 9:58 a.m.
On Fri, Apr 26, 2013 at 11:53:49AM +0200, Alexander Graf wrote:
> 
> On 26.04.2013, at 11:38, Aurelien Jarno wrote:
> 
> > On Fri, Apr 26, 2013 at 09:50:31AM +0200, Alexander Graf wrote:
> >> 
> >> On 20.04.2013, at 20:56, Aurelien Jarno wrote:
> >> 
> >>> Needed for Power ISA version 2.05 compliance.
> >>> 
> >>> Reviewed-by: Richard Henderson <rth@twiddle.net>
> >>> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
> >>> ---
> >>> target-ppc/translate.c |   38 ++++++++++++++++++++++++++++++++++++++
> >>> 1 file changed, 38 insertions(+)
> >>> 
> >>> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> >>> index 6bee6db..977f9ef 100644
> >>> --- a/target-ppc/translate.c
> >>> +++ b/target-ppc/translate.c
> >>> @@ -1458,6 +1458,42 @@ static void gen_popcntd(DisasContext *ctx)
> >>> }
> >>> #endif
> >>> 
> >>> +/* prtyw: PowerPC 2.05 specification */
> >>> +static void gen_prtyw(DisasContext *ctx)
> >>> +{
> >>> +    TCGv ra = cpu_gpr[rA(ctx->opcode)];
> >>> +    TCGv rs = cpu_gpr[rS(ctx->opcode)];
> >>> +    TCGv t0 = tcg_temp_new();
> >>> +    tcg_gen_shri_tl(t0, rs, 16);
> >>> +    tcg_gen_xor_tl(ra, rs, t0);
> >>> +    tcg_gen_shri_tl(t0, ra, 8);
> >>> +    tcg_gen_xor_tl(ra, ra, t0);
> >>> +#if defined(TARGET_PPC64)
> >>> +    tcg_gen_andi_tl(ra, ra, 0x100000001);
> >> 
> >> This will break on 32-bit host systems. Let me fix it to ULL for you :). In fact, any reason for the #ifdef here? We could just always pass 0x100000001ULL and have the target_ulong cast take the upper 32bit away, no?
> > 
> > Good catch. The #ifdef version matches the instruction definition in the
> > manual, but for QEMU I agree a version using a cast with target_ulong
> > looks better. Should I send a new patch?
> 
> I already fixed it up while applying the patch, thanks :)

Ok, thanks.

Patch

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 6bee6db..977f9ef 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -1458,6 +1458,42 @@  static void gen_popcntd(DisasContext *ctx)
 }
 #endif
 
+/* prtyw: PowerPC 2.05 specification */
+static void gen_prtyw(DisasContext *ctx)
+{
+    TCGv ra = cpu_gpr[rA(ctx->opcode)];
+    TCGv rs = cpu_gpr[rS(ctx->opcode)];
+    TCGv t0 = tcg_temp_new();
+    tcg_gen_shri_tl(t0, rs, 16);
+    tcg_gen_xor_tl(ra, rs, t0);
+    tcg_gen_shri_tl(t0, ra, 8);
+    tcg_gen_xor_tl(ra, ra, t0);
+#if defined(TARGET_PPC64)
+    tcg_gen_andi_tl(ra, ra, 0x100000001);
+#else
+    tcg_gen_andi_tl(ra, ra, 1);
+#endif
+    tcg_temp_free(t0);
+}
+
+#if defined(TARGET_PPC64)
+/* prtyd: PowerPC 2.05 specification */
+static void gen_prtyd(DisasContext *ctx)
+{
+    TCGv ra = cpu_gpr[rA(ctx->opcode)];
+    TCGv rs = cpu_gpr[rS(ctx->opcode)];
+    TCGv t0 = tcg_temp_new();
+    tcg_gen_shri_tl(t0, rs, 32);
+    tcg_gen_xor_tl(ra, rs, t0);
+    tcg_gen_shri_tl(t0, ra, 16);
+    tcg_gen_xor_tl(ra, ra, t0);
+    tcg_gen_shri_tl(t0, ra, 8);
+    tcg_gen_xor_tl(ra, ra, t0);
+    tcg_gen_andi_tl(ra, ra, 1);
+    tcg_temp_free(t0);
+}
+#endif
+
 #if defined(TARGET_PPC64)
 /* extsw & extsw. */
 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
@@ -8489,9 +8525,11 @@  GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB),
 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
+GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
 #if defined(TARGET_PPC64)
 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
+GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
 #endif
 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),