From patchwork Fri Apr 19 10:47:43 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: chenhui zhao X-Patchwork-Id: 237909 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [IPv6:::1]) by ozlabs.org (Postfix) with ESMTP id CA1CF2C0BA8 for ; Fri, 19 Apr 2013 20:56:19 +1000 (EST) Received: from va3outboundpool.messaging.microsoft.com (va3ehsobe003.messaging.microsoft.com [216.32.180.13]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (Client CN "mail.global.frontbridge.com", Issuer "Microsoft Secure Server Authority" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 8F8F82C026E for ; Fri, 19 Apr 2013 20:48:29 +1000 (EST) Received: from mail74-va3-R.bigfish.com (10.7.14.232) by VA3EHSOBE006.bigfish.com (10.7.40.26) with Microsoft SMTP Server id 14.1.225.23; Fri, 19 Apr 2013 10:48:27 +0000 Received: from mail74-va3 (localhost [127.0.0.1]) by mail74-va3-R.bigfish.com (Postfix) with ESMTP id 18C3D3C0871; Fri, 19 Apr 2013 10:48:27 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1f42h1fc6h1ee6h1de0h1fdah1202h1e76h1d1ah1d2ahzz8275bhz2dh2a8h668h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h1354h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1155h) Received: from mail74-va3 (localhost.localdomain [127.0.0.1]) by mail74-va3 (MessageSwitch) id 1366368505416226_26687; Fri, 19 Apr 2013 10:48:25 +0000 (UTC) Received: from VA3EHSMHS028.bigfish.com (unknown [10.7.14.229]) by mail74-va3.bigfish.com (Postfix) with ESMTP id 5FD9F180097; Fri, 19 Apr 2013 10:48:25 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by VA3EHSMHS028.bigfish.com (10.7.99.38) with Microsoft SMTP Server (TLS) id 14.1.225.23; Fri, 19 Apr 2013 10:48:25 +0000 Received: from az84smr01.freescale.net (10.64.34.197) by 039-SN1MMR1-001.039d.mgd.msft.net (10.84.1.13) with Microsoft SMTP Server (TLS) id 14.2.328.11; Fri, 19 Apr 2013 10:48:24 +0000 Received: from localhost.localdomain ([10.193.20.174]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id r3JAm5TU028249; Fri, 19 Apr 2013 03:48:22 -0700 From: Zhao Chenhui To: Subject: [PATCH v2 10/15] powerpc/85xx: fix 64-bit support for cpu hotplug Date: Fri, 19 Apr 2013 18:47:43 +0800 Message-ID: <1366368468-29143-10-git-send-email-chenhui.zhao@freescale.com> X-Mailer: git-send-email 1.7.3 In-Reply-To: <1366368468-29143-1-git-send-email-chenhui.zhao@freescale.com> References: <1366368468-29143-1-git-send-email-chenhui.zhao@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com Cc: linux-kernel@vger.kernel.org X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" From: Chen-Hui Zhao * The paca[cpu].cpu_start is used as a signal to indicate if the cpu should start. So it should be cleard in .cpu_die(). * The limit memory routine only needs to be ran once at boot time by the boot cpu. Prevent other cpus running it again. * Rearrange the code segment in smp_85xx_kick_cpu() to share codes between PPC64 and PPC32 as far as possible. Signed-off-by: Zhao Chenhui Signed-off-by: Li Yang Signed-off-by: Andy Fleming --- arch/powerpc/Kconfig | 2 +- arch/powerpc/kernel/smp.c | 3 +++ arch/powerpc/mm/tlb_nohash.c | 6 ++++-- arch/powerpc/platforms/85xx/smp.c | 23 +++++++++++------------ 4 files changed, 19 insertions(+), 15 deletions(-) diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 0ad6e30..aa5794b 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -347,7 +347,7 @@ config SWIOTLB config HOTPLUG_CPU bool "Support for enabling/disabling CPUs" depends on SMP && HOTPLUG && (PPC_PSERIES || \ - PPC_PMAC || PPC_POWERNV || PPC_85xx) + PPC_PMAC || PPC_POWERNV || FSL_SOC_BOOKE) ---help--- Say Y here to be able to disable and re-enable individual CPUs at runtime on SMP machines. diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c index 386c7ea..c8aa739 100644 --- a/arch/powerpc/kernel/smp.c +++ b/arch/powerpc/kernel/smp.c @@ -401,6 +401,9 @@ void generic_cpu_die(unsigned int cpu) smp_rmb(); if (per_cpu(cpu_state, cpu) == CPU_DEAD) { platform_cpu_die(cpu); +#ifdef CONFIG_PPC64 + paca[cpu].cpu_start = 0; +#endif return; } msleep(100); diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c index 6888cad..de7bf06 100644 --- a/arch/powerpc/mm/tlb_nohash.c +++ b/arch/powerpc/mm/tlb_nohash.c @@ -627,8 +627,10 @@ static void __early_init_mmu(int boot_cpu) num_cams = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) / 4; linear_map_top = map_mem_in_cams(linear_map_top, num_cams); - /* limit memory so we dont have linear faults */ - memblock_enforce_memory_limit(linear_map_top); + if (boot_cpu) { + /* limit memory so we dont have linear faults */ + memblock_enforce_memory_limit(linear_map_top); + } patch_exception(0x1c0, exc_data_tlb_miss_bolted_book3e); patch_exception(0x1e0, exc_instruction_tlb_miss_bolted_book3e); diff --git a/arch/powerpc/platforms/85xx/smp.c b/arch/powerpc/platforms/85xx/smp.c index 6eae2e0..74d8cde 100644 --- a/arch/powerpc/platforms/85xx/smp.c +++ b/arch/powerpc/platforms/85xx/smp.c @@ -251,10 +251,6 @@ static int __cpuinit smp_85xx_kick_cpu(int nr) spin_table = phys_to_virt(*cpu_rel_addr); local_irq_save(flags); -#ifdef CONFIG_PPC32 -#ifdef CONFIG_HOTPLUG_CPU - /* Corresponding to generic_set_cpu_dead() */ - generic_set_cpu_up(nr); if (system_state == SYSTEM_RUNNING) { /* @@ -298,12 +294,19 @@ static int __cpuinit smp_85xx_kick_cpu(int nr) /* clear the acknowledge status */ __secondary_hold_acknowledge = -1; } -#endif flush_spin_table(spin_table); out_be32(&spin_table->pir, hw_cpu); +#ifdef CONFIG_PPC32 out_be32(&spin_table->addr_l, __pa(__early_start)); +#else + out_be32(&spin_table->addr_h, + __pa(*(u64 *)generic_secondary_smp_init) >> 32); + out_be32(&spin_table->addr_l, + __pa(*(u64 *)generic_secondary_smp_init) & 0xffffffff); +#endif flush_spin_table(spin_table); +#ifdef CONFIG_PPC32 /* Wait a bit for the CPU to ack. */ if (!spin_event_timeout(__secondary_hold_acknowledge == hw_cpu, 10000, 100)) { @@ -312,18 +315,14 @@ static int __cpuinit smp_85xx_kick_cpu(int nr) ret = -ENOENT; goto out; } -out: #else smp_generic_kick_cpu(nr); - - flush_spin_table(spin_table); - out_be32(&spin_table->pir, hw_cpu); - out_be64((u64 *)(&spin_table->addr_h), - __pa((u64)*((unsigned long long *)generic_secondary_smp_init))); - flush_spin_table(spin_table); #endif + /* Corresponding to generic_set_cpu_dead() */ + generic_set_cpu_up(nr); cur_booting_core = hw_cpu; +out: local_irq_restore(flags); if (ioremappable)