From patchwork Fri Apr 19 09:34:49 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greta Yorsh X-Patchwork-Id: 237891 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "localhost", Issuer "www.qmailtoaster.com" (not verified)) by ozlabs.org (Postfix) with ESMTPS id ED45F2C0545 for ; Fri, 19 Apr 2013 19:35:10 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; q=dns; s=default; b=i1o6yI0RDad8UUwrjPb9MqZqJSaI27/Dm4jKtCY2CTTA3HSoVI QCymMLswn9HQepfg47p0wfzJ1RAbrN/r5h0jz7UlPdr9sbZMFqXJ4SJKbdlAyXnJ nel8zBQvw1DTqEHvArQv4BdWtsrZWqd1jqIZDyq7MJWZSTqPryYlhlCds= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; s= default; bh=95Ax3sXihe3LIJQO4bZDiipCyIs=; b=c17E+byJ4f2MOQE34WIV ezh7r4ig6Xh9OEIiD/0Patj9/AunE1QWdFyXnxLa8GG+tFZKEqndeUyN7pXzknDi FbL/H613tcOodaufObYlHjbtn9BJvN2g3y+bZB+YLHlETHyy2gj7OxXh1F42JZL1 5VNxt1OKV6n19RQghqXuW34= Received: (qmail 14391 invoked by alias); 19 Apr 2013 09:35:04 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 14375 invoked by uid 89); 19 Apr 2013 09:35:04 -0000 X-Spam-SWARE-Status: No, score=-1.4 required=5.0 tests=AWL, BAYES_00, KHOP_RCVD_UNTRUST, MSGID_MULTIPLE_AT, RCVD_IN_DNSWL_LOW, TW_QE autolearn=no version=3.3.1 Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Fri, 19 Apr 2013 09:35:03 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Fri, 19 Apr 2013 10:35:00 +0100 Received: from e103227vm ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.0); Fri, 19 Apr 2013 10:34:58 +0100 From: "Greta Yorsh" To: "GCC Patches" Cc: , "Richard Earnshaw" , "Ramana Radhakrishnan" Subject: [PATCH, ARM] Fix PR56797 Date: Fri, 19 Apr 2013 10:34:49 +0100 Message-ID: <000801ce3ce1$23fbdd60$6bf39820$@yorsh@arm.com> MIME-Version: 1.0 X-MC-Unique: 113041910350011801 X-Virus-Found: No Fix PR56797 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56797 The problem is that peephole optimizer thinks it can generate an ldm, but the pattern for ldm no longer matches, because after r188738 it requires that if one of the destination registers is SP then the base register must be SP, and it's not SP in the test case. The test case fails on armv5t but doesn't fail on armv6t2 or armv7-a because peephole doesn't trigger there (because there is a different epilogue sequence). It looks like a latent problem for other architecture or CPUs. This patch adds this condition to the peephole optimizer. No regression on qemu for arm-none-eabi and fixes the test reported in the PR. I couldn't minimize the test sufficiently to include it in the testsuite. Ok for trunk? Thanks, Greta gcc/ 2013-04-18 Greta Yorsh PR target/56797 * config/arm/arm.c (load_multiple_sequence): Require SP as base register for loads if SP is in the register list. diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index d00849c..60fef78 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -10347,6 +10347,13 @@ load_multiple_sequence (rtx *operands, int nops, int *regs, int *saved_order, || (i != nops - 1 && unsorted_regs[i] == base_reg)) return 0; + /* Don't allow SP to be loaded unless it is also the base + register. It guarantees that SP is reset correctly when + an LDM instruction is interruptted. Otherwise, we might + end up with a corrupt stack. */ + if (unsorted_regs[i] == SP_REGNUM && base_reg != SP_REGNUM) + return 0; + unsorted_offsets[i] = INTVAL (offset); if (i == 0 || unsorted_offsets[i] < unsorted_offsets[order[0]]) order[0] = i;