From patchwork Fri Apr 19 02:09:31 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Crosthwaite X-Patchwork-Id: 237811 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 21A712C04C3 for ; Fri, 19 Apr 2013 12:12:06 +1000 (EST) Received: from localhost ([::1]:53403 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UT0o0-0005UY-9L for incoming@patchwork.ozlabs.org; Thu, 18 Apr 2013 22:12:04 -0400 Received: from eggs.gnu.org ([208.118.235.92]:58392) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UT0nZ-0005RX-EV for qemu-devel@nongnu.org; Thu, 18 Apr 2013 22:11:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UT0nY-0004eH-BF for qemu-devel@nongnu.org; Thu, 18 Apr 2013 22:11:37 -0400 Received: from mail-da0-x235.google.com ([2607:f8b0:400e:c00::235]:44260) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UT0nY-0004e2-3f for qemu-devel@nongnu.org; Thu, 18 Apr 2013 22:11:36 -0400 Received: by mail-da0-f53.google.com with SMTP id n34so1672400dal.26 for ; Thu, 18 Apr 2013 19:11:35 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references:x-gm-message-state; bh=mkulZEUza4SZMuX0o2zv76t3cvQzL3KqSYVa6BNrSKk=; b=O80SA7dpMYOeA6+xMoPCgNEENr/G199RPPpBgq3mYsVh2mFyisT2QHD3GNylTpAFqj X7MHQLdmwuwCw2sISN2+HqKMZ/hQOHjfKHcys+oGlZw9/TXQZ9MwDME3DaaG3NYj+PAb C8w7EAhnh0HfsptMjdDVnRzzoCD4owmNQjiX5zDj94tv5XxIoqR8TFtMJM2LGGed6jO8 6fwP2Yvgf2K4cY90swVKvdT3OQSm4qvsdfGvy8qVj5A9Zbj0pPJP9baKz/y+vzcFJNvb fO0RyteLyu8r3vM9EM8pfp1TaafUOeUcrTJWdugZ4bGcj81yjwqbD5ggjOAvtOgmjOLS jR5g== X-Received: by 10.66.12.39 with SMTP id v7mr1830860pab.13.1366337495412; Thu, 18 Apr 2013 19:11:35 -0700 (PDT) Received: from localhost ([149.199.62.254]) by mx.google.com with ESMTPS id g8sm12823737pae.7.2013.04.18.19.11.33 (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Thu, 18 Apr 2013 19:11:34 -0700 (PDT) From: peter.crosthwaite@xilinx.com To: qemu-devel@nongnu.org Date: Fri, 19 Apr 2013 12:09:31 +1000 Message-Id: <444ee069e965a210a881db9913335156b2c332e0.1366335998.git.peter.crosthwaite@xilinx.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: References: X-Gm-Message-State: ALoCoQn4biX8GKbUt9hITtS+rMEuTLBpFE3xGFAgmGxLrKclnRlpP5nqdAjzdsUpQOMn0iHKu8S8 X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c00::235 Cc: peter.maydell@linaro.org Subject: [Qemu-devel] [PATCH for-1.5 v2 10/15] xilinx_spips: Fix CTRL register RW bits X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Peter Crosthwaite The CTRL register was RAZ/WI on some of the RW bits. Even though the function behind these bits is invalid in QEMU, they should still be guest accessible. Fix. Signed-off-by: Peter Crosthwaite --- changed from v1 Macroified magic number (PMM review) hw/ssi/xilinx_spips.c | 5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index bc86375..b5997c1 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -56,6 +56,7 @@ #define CLK_PH (1 << 2) #define CLK_POL (1 << 1) #define MODE_SEL (1 << 0) +#define R_CONFIG_RSVD (0x7bf40000) /* interrupt mechanism */ #define R_INTR_STATUS (0x04 / 4) @@ -355,7 +356,7 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, addr >>= 2; switch (addr) { case R_CONFIG: - mask = 0x0002FFFF; + mask = ~(R_CONFIG_RSVD | MAN_START_COM); break; case R_INTR_STATUS: ret = s->regs[addr] & IXR_ALL; @@ -415,7 +416,7 @@ static void xilinx_spips_write(void *opaque, hwaddr addr, addr >>= 2; switch (addr) { case R_CONFIG: - mask = 0x0002FFFF; + mask = ~(R_CONFIG_RSVD | MAN_START_COM); if (value & MAN_START_COM) { man_start_com = 1; }