From patchwork Fri Apr 19 02:08:52 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Crosthwaite X-Patchwork-Id: 237810 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 078082C021A for ; Fri, 19 Apr 2013 12:11:34 +1000 (EST) Received: from localhost ([::1]:52670 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UT0nU-00056T-4t for incoming@patchwork.ozlabs.org; Thu, 18 Apr 2013 22:11:32 -0400 Received: from eggs.gnu.org ([208.118.235.92]:58259) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UT0mw-0004hn-2M for qemu-devel@nongnu.org; Thu, 18 Apr 2013 22:10:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UT0mu-0004Oo-WC for qemu-devel@nongnu.org; Thu, 18 Apr 2013 22:10:57 -0400 Received: from mail-pd0-f176.google.com ([209.85.192.176]:50358) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UT0mu-0004Oa-H7 for qemu-devel@nongnu.org; Thu, 18 Apr 2013 22:10:56 -0400 Received: by mail-pd0-f176.google.com with SMTP id r11so1904256pdi.7 for ; Thu, 18 Apr 2013 19:10:55 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references:x-gm-message-state; bh=HV3yx7CCLuopVc7OUIzKjQr910bg6LbRZARtcPlgPLo=; b=p1jF8y0wVdVsY/Y6YnCRghRoccE2g+vw9zJiBNOQFkpbdYum8c0lx/1J1cszumbUIV gO/xAIc0MVxhkVAQo/1BXkhP0YieXSOdjveQ1GQrM4lRwNVtFsnMphlnkg40sqgpdEJ3 jSiSm91VoM5gKmtr3PDv1iHPkC5YLsSRNcWdE51xILRjqEGJ+8I8VSPOAkI2zRwObDI9 iLRAYlqDNQ1YHT6ai+PoRzILaEnPn6NK55wA2A7pcurSDXtOCBxZsjrphZgd6+CMpMW0 We9+a3zQcQrzSFQ+7Fb03Mc0PZBipS8VVTiRh6jfkoIdTUgdW5+aQxoJTh4Pk0fFIWTp YuNw== X-Received: by 10.68.179.101 with SMTP id df5mr15882510pbc.199.1366337455912; Thu, 18 Apr 2013 19:10:55 -0700 (PDT) Received: from localhost ([149.199.62.254]) by mx.google.com with ESMTPS id wi6sm11597088pbc.22.2013.04.18.19.10.53 (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Thu, 18 Apr 2013 19:10:55 -0700 (PDT) From: peter.crosthwaite@xilinx.com To: qemu-devel@nongnu.org Date: Fri, 19 Apr 2013 12:08:52 +1000 Message-Id: X-Mailer: git-send-email 1.7.0.4 In-Reply-To: References: X-Gm-Message-State: ALoCoQk37fV+eOuDM7VeAREsbjGiEsWyS9arDHFZ44oYx5CSon61VygcmQoubTaS4zsVQEskQVxd X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 209.85.192.176 Cc: peter.maydell@linaro.org Subject: [Qemu-devel] [PATCH for-1.5 v2 09/15] xilinx_spips: lqspi: Dont touch config register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Peter Crosthwaite The LQSPI mode is supposed to work via the automatic CS mode feature rather than manipulate CS lines itself. Now that auto CS is implemented remove LQSPIs CS mode override logic. There is still a need to manipulate the U_PAGE bit in LQSPI config register to implement dual-stack mode however. Signed-off-by: Peter Crosthwaite --- This patch in new as of v2 hw/ssi/xilinx_spips.c | 12 ++++++------ 1 files changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 7699562..bc86375 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -512,16 +512,16 @@ lqspi_read(void *opaque, hwaddr addr, unsigned int size) int flash_addr = (addr / num_effective_busses(s)); int slave = flash_addr >> LQSPI_ADDRESS_BITS; int cache_entry = 0; + uint32_t u_page_save = s->regs[R_LQSPI_STS] & ~LQSPI_CFG_U_PAGE; + + s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE; + s->regs[R_LQSPI_STS] |= slave ? LQSPI_CFG_U_PAGE : 0; DB_PRINT("config reg status: %08x\n", s->regs[R_LQSPI_CFG]); fifo8_reset(&s->tx_fifo); fifo8_reset(&s->rx_fifo); - s->regs[R_CONFIG] &= ~CS; - s->regs[R_CONFIG] |= ((~(1 << slave) << CS_SHIFT) & CS) | MANUAL_CS; - xilinx_spips_update_cs_lines(s); - /* instruction */ DB_PRINT("pushing read instruction: %02x\n", (uint8_t)(s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE)); @@ -555,9 +555,9 @@ lqspi_read(void *opaque, hwaddr addr, unsigned int size) rx_data_bytes(s, &q->lqspi_buf[cache_entry], 4); cache_entry++; } - xilinx_spips_update_cs_lines(s); - s->regs[R_CONFIG] |= CS; + s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE; + s->regs[R_LQSPI_STS] |= u_page_save; xilinx_spips_update_cs_lines(s); q->lqspi_cached_addr = addr;