[for-1.5,v2,09/15] xilinx_spips: lqspi: Dont touch config register

Submitted by Peter Crosthwaite on April 19, 2013, 2:08 a.m.

Details

Message ID af79cc1eee15c7af53df34bbc299fea3f6d016d5.1366335998.git.peter.crosthwaite@xilinx.com
State New
Headers show

Commit Message

Peter Crosthwaite April 19, 2013, 2:08 a.m.
From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>

The LQSPI mode is supposed to work via the automatic CS mode feature
rather than manipulate CS lines itself. Now that auto CS is implemented
remove LQSPIs CS mode override logic. There is still a need to
manipulate the U_PAGE bit in LQSPI config register to implement
dual-stack mode however.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
---
This patch in new as of v2

 hw/ssi/xilinx_spips.c |   12 ++++++------
 1 files changed, 6 insertions(+), 6 deletions(-)

Patch hide | download patch | download mbox

diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
index 7699562..bc86375 100644
--- a/hw/ssi/xilinx_spips.c
+++ b/hw/ssi/xilinx_spips.c
@@ -512,16 +512,16 @@  lqspi_read(void *opaque, hwaddr addr, unsigned int size)
         int flash_addr = (addr / num_effective_busses(s));
         int slave = flash_addr >> LQSPI_ADDRESS_BITS;
         int cache_entry = 0;
+        uint32_t u_page_save = s->regs[R_LQSPI_STS] & ~LQSPI_CFG_U_PAGE;
+
+        s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE;
+        s->regs[R_LQSPI_STS] |= slave ? LQSPI_CFG_U_PAGE : 0;
 
         DB_PRINT("config reg status: %08x\n", s->regs[R_LQSPI_CFG]);
 
         fifo8_reset(&s->tx_fifo);
         fifo8_reset(&s->rx_fifo);
 
-        s->regs[R_CONFIG] &= ~CS;
-        s->regs[R_CONFIG] |= ((~(1 << slave) << CS_SHIFT) & CS) | MANUAL_CS;
-        xilinx_spips_update_cs_lines(s);
-
         /* instruction */
         DB_PRINT("pushing read instruction: %02x\n",
                  (uint8_t)(s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE));
@@ -555,9 +555,9 @@  lqspi_read(void *opaque, hwaddr addr, unsigned int size)
             rx_data_bytes(s, &q->lqspi_buf[cache_entry], 4);
             cache_entry++;
         }
-        xilinx_spips_update_cs_lines(s);
 
-        s->regs[R_CONFIG] |= CS;
+        s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE;
+        s->regs[R_LQSPI_STS] |= u_page_save;
         xilinx_spips_update_cs_lines(s);
 
         q->lqspi_cached_addr = addr;