From patchwork Fri Apr 19 02:06:52 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Crosthwaite X-Patchwork-Id: 237807 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id D4F2A2C0216 for ; Fri, 19 Apr 2013 12:09:19 +1000 (EST) Received: from localhost ([::1]:48153 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UT0lK-0002O0-0d for incoming@patchwork.ozlabs.org; Thu, 18 Apr 2013 22:09:18 -0400 Received: from eggs.gnu.org ([208.118.235.92]:57835) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UT0l1-0002IY-8r for qemu-devel@nongnu.org; Thu, 18 Apr 2013 22:09:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UT0l0-0003ZR-7R for qemu-devel@nongnu.org; Thu, 18 Apr 2013 22:08:59 -0400 Received: from mail-pd0-f174.google.com ([209.85.192.174]:43580) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UT0kz-0003YQ-Q3 for qemu-devel@nongnu.org; Thu, 18 Apr 2013 22:08:57 -0400 Received: by mail-pd0-f174.google.com with SMTP id p12so1908205pdj.33 for ; Thu, 18 Apr 2013 19:08:57 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references:x-gm-message-state; bh=cmKmyXo47rxCjbdtWcoosb8WlsGntMSQFHwA38faz3c=; b=YBVEXjda4Y+KeFD84d5N80h9Wg2jh7ceevLadBoWcBRRNV+LwRrefWB4veIFfo8Prb fCskXCO7jK2uHz+JxjU6TiB7+Qap9VmoaKequxOp+nnldRY12i1uD6U7PdV25oinhx5X KqHfxYDJicc4ZfZVRbQIPCHuW377upgiuEyiPWZzOrtzFGZJlkirYrNG0iRdqP2Rvgs7 lcMT4s4/OAUbmsOZeBv4HYpFFHQoiRNQDCpa6oo68V4jfeBU/8I7yd4XZfiyP+1CjXRG obANEv0lkOm20YwuvIsMlKciNCDUSnwR4ERmG2MDam0gPbGhcBt+EnqqwI19JhkiXsDi SGTQ== X-Received: by 10.67.10.133 with SMTP id ea5mr15824422pad.135.1366337337148; Thu, 18 Apr 2013 19:08:57 -0700 (PDT) Received: from localhost ([149.199.62.254]) by mx.google.com with ESMTPS id xz4sm11599690pbb.18.2013.04.18.19.08.54 (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Thu, 18 Apr 2013 19:08:56 -0700 (PDT) From: peter.crosthwaite@xilinx.com To: qemu-devel@nongnu.org Date: Fri, 19 Apr 2013 12:06:52 +1000 Message-Id: <0890ab958dbecc05faeae7bcdb4a5051f0625875.1366335998.git.peter.crosthwaite@xilinx.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: References: X-Gm-Message-State: ALoCoQlEAToE/lb3z8T93fOj1b/jli4M0XBDfY7XR6QiVMBxwzYJMvqdRcYP3k9wNSTg5HduIjQI X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 209.85.192.174 Cc: peter.maydell@linaro.org Subject: [Qemu-devel] [PATCH for-1.5 v2 06/15] xilinx_spips: Trash LQ page cache on mode change X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Peter Crosthwaite Invalidate the LQSPI cached page when transitioning into LQSPI mode. Otherwise there is a possibility that the controller will return stale data to the guest when transitioning back to LQ_MODE after a page program. Signed-off-by: Peter Crosthwaite --- changed from v1: Re-implemented using separate SPI/QSPI write handlers. hw/ssi/xilinx_spips.c | 26 +++++++++++++++++++++++++- 1 files changed, 25 insertions(+), 1 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index e351cb2..6d38111 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -165,6 +165,8 @@ typedef struct { typedef struct XilinxSPIPSClass { SysBusDeviceClass parent_class; + const MemoryRegionOps *reg_ops; + uint32_t rx_fifo_size; uint32_t tx_fifo_size; } XilinxSPIPSClass; @@ -446,6 +448,7 @@ static void xilinx_spips_write(void *opaque, hwaddr addr, case R_TXD3: tx_data_bytes(s, (uint32_t)value, 3); goto no_reg_update; + break; } s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask); no_reg_update: @@ -462,6 +465,25 @@ static const MemoryRegionOps spips_ops = { .endianness = DEVICE_LITTLE_ENDIAN, }; +static void xilinx_qspips_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size) +{ + XilinxQSPIPS *q = XILINX_QSPIPS(opaque); + + xilinx_spips_write(opaque, addr, value, size); + addr >>= 2; + + if (addr == R_LQSPI_CFG) { + q->lqspi_cached_addr = ~0ULL; + } +} + +static const MemoryRegionOps qspips_ops = { + .read = xilinx_spips_read, + .write = xilinx_qspips_write, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + #define LQSPI_CACHE_SIZE 1024 static uint64_t @@ -565,7 +587,7 @@ static void xilinx_spips_realize(DeviceState *dev, Error **errp) sysbus_init_irq(sbd, &s->cs_lines[i]); } - memory_region_init_io(&s->iomem, &spips_ops, s, "spi", R_MAX*4); + memory_region_init_io(&s->iomem, xsc->reg_ops, s, "spi", R_MAX*4); sysbus_init_mmio(sbd, &s->iomem); s->irqline = -1; @@ -629,6 +651,7 @@ static void xilinx_qspips_class_init(ObjectClass *klass, void * data) XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass); dc->realize = xilinx_qspips_realize; + xsc->reg_ops = &qspips_ops; xsc->rx_fifo_size = RXFF_A_Q; xsc->tx_fifo_size = TXFF_A_Q; } @@ -643,6 +666,7 @@ static void xilinx_spips_class_init(ObjectClass *klass, void *data) dc->props = xilinx_spips_properties; dc->vmsd = &vmstate_xilinx_spips; + xsc->reg_ops = &spips_ops; xsc->rx_fifo_size = RXFF_A; xsc->tx_fifo_size = TXFF_A; }