From patchwork Fri Apr 19 02:03:29 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Crosthwaite X-Patchwork-Id: 237802 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 5326A2C021A for ; Fri, 19 Apr 2013 12:06:08 +1000 (EST) Received: from localhost ([::1]:40625 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UT0iE-0006l5-G5 for incoming@patchwork.ozlabs.org; Thu, 18 Apr 2013 22:06:06 -0400 Received: from eggs.gnu.org ([208.118.235.92]:57076) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UT0hj-0006hG-Qv for qemu-devel@nongnu.org; Thu, 18 Apr 2013 22:05:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UT0hi-0002gJ-Nh for qemu-devel@nongnu.org; Thu, 18 Apr 2013 22:05:35 -0400 Received: from mail-pa0-f46.google.com ([209.85.220.46]:38505) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UT0hi-0002gD-F5 for qemu-devel@nongnu.org; Thu, 18 Apr 2013 22:05:34 -0400 Received: by mail-pa0-f46.google.com with SMTP id lb1so1953537pab.33 for ; Thu, 18 Apr 2013 19:05:33 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references:x-gm-message-state; bh=ntMstT/VcLKfPYM5VZvpQGJMhzTA9/aGrB1O/LzYEoc=; b=Nm7TJ/NN5yx7b74pbpUHqtEBeO2G6LjGJA9nJuIS7fFrV/NSapSLUDyabyS8h02P2j sNPht6NMYfRunsxQrs/OCcQ+EQqOGMu7Z2Xx7sFemRHCb8Xl+Fr+TWFfc2V3IJJxnk4v wCqoGQatUYULFqrQykJ2hJao7N2YfR9tFH1atpSSpxgmxpsyiFtVJ1OneMdzTqxIYk7B teLsOPjW4zTht1QRVys/7FyDLZONYJiQkJu4L1Wpml41VuNgcO/fWGwgwtsy2XANSUsH 5kpMPczXJgxqRUFTvYFxgM9lnGBRGXc/8ZM8Xfwy5PYtcR7v5zmeNm47gDXRdi+Pkh8A WAAQ== X-Received: by 10.66.220.10 with SMTP id ps10mr2891449pac.117.1366337133789; Thu, 18 Apr 2013 19:05:33 -0700 (PDT) Received: from localhost ([149.199.62.254]) by mx.google.com with ESMTPS id uy3sm11611189pbc.7.2013.04.18.19.05.30 (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Thu, 18 Apr 2013 19:05:32 -0700 (PDT) From: peter.crosthwaite@xilinx.com To: qemu-devel@nongnu.org Date: Fri, 19 Apr 2013 12:03:29 +1000 Message-Id: <975cd98a93b56befa99802766dfbcb78c8de86d9.1366335998.git.peter.crosthwaite@xilinx.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: References: X-Gm-Message-State: ALoCoQkzXvwkEbZnWnIwIRvFPUGJRovUPKpwJx3FN5pahcs/qVn4QLQOSMsi5Uj4OLCdT6lWLj+7 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 209.85.220.46 Cc: peter.maydell@linaro.org Subject: [Qemu-devel] [PATCH for-1.5 v2 01/15] xilinx_spips: seperate SPI and QSPI as two classes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Peter Crosthwaite Make SPI and QSPI different classes. QSPIPS is setup as a child of SPIPS. Only QSPI has the LQSPI functionality, so move all that to the child class. Signed-off-by: Peter Crosthwaite --- Changed from v2: User parent_obj as appropriate for QOM parents (PMM review) Changed from v1: Fixed compile bug (s/XILINX_SPIPS/XILINX_QSPIPS on QOM cast) hw/arm/xilinx_zynq.c | 2 +- hw/ssi/xilinx_spips.c | 69 +++++++++++++++++++++++++++++++++++++++---------- 2 files changed, 56 insertions(+), 15 deletions(-) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 41505c3..4602a6f 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -66,7 +66,7 @@ static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq, int num_busses = is_qspi ? NUM_QSPI_BUSSES : 1; int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES; - dev = qdev_create(NULL, "xilinx,spips"); + dev = qdev_create(NULL, is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi"); qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1); qdev_prop_set_uint8(dev, "num-ss-bits", num_ss); qdev_prop_set_uint8(dev, "num-busses", num_busses); diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index b2397f4..734adf0 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -129,7 +129,8 @@ typedef enum { } FlashCMD; typedef struct { - SysBusDevice busdev; + SysBusDevice parent_obj; + MemoryRegion iomem; MemoryRegion mmlqspi; @@ -149,15 +150,23 @@ typedef struct { uint8_t num_txrx_bytes; uint32_t regs[R_MAX]; +} XilinxSPIPS; + +typedef struct { + XilinxSPIPS parent_obj; uint32_t lqspi_buf[LQSPI_CACHE_SIZE]; hwaddr lqspi_cached_addr; -} XilinxSPIPS; +} XilinxQSPIPS; + -#define TYPE_XILINX_SPIPS "xilinx,spips" +#define TYPE_XILINX_SPIPS "xlnx.ps7-spi" +#define TYPE_XILINX_QSPIPS "xlnx.ps7-qspi" #define XILINX_SPIPS(obj) \ OBJECT_CHECK(XilinxSPIPS, (obj), TYPE_XILINX_SPIPS) +#define XILINX_QSPIPS(obj) \ + OBJECT_CHECK(XilinxQSPIPS, (obj), TYPE_XILINX_QSPIPS) static inline int num_effective_busses(XilinxSPIPS *s) { @@ -436,11 +445,12 @@ static uint64_t lqspi_read(void *opaque, hwaddr addr, unsigned int size) { int i; + XilinxQSPIPS *q = opaque; XilinxSPIPS *s = opaque; - if (addr >= s->lqspi_cached_addr && - addr <= s->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) { - return s->lqspi_buf[(addr - s->lqspi_cached_addr) >> 2]; + if (addr >= q->lqspi_cached_addr && + addr <= q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) { + return q->lqspi_buf[(addr - q->lqspi_cached_addr) >> 2]; } else { int flash_addr = (addr / num_effective_busses(s)); int slave = flash_addr >> LQSPI_ADDRESS_BITS; @@ -484,14 +494,14 @@ lqspi_read(void *opaque, hwaddr addr, unsigned int size) for (i = 0; i < LQSPI_CACHE_SIZE / 4; ++i) { tx_data_bytes(s, 0, 4); xilinx_spips_flush_txfifo(s); - rx_data_bytes(s, &s->lqspi_buf[cache_entry], 4); + rx_data_bytes(s, &q->lqspi_buf[cache_entry], 4); cache_entry++; } s->regs[R_CONFIG] |= CS; xilinx_spips_update_cs_lines(s); - s->lqspi_cached_addr = addr; + q->lqspi_cached_addr = addr; return lqspi_read(opaque, addr, size); } } @@ -511,7 +521,7 @@ static void xilinx_spips_realize(DeviceState *dev, Error **errp) SysBusDevice *sbd = SYS_BUS_DEVICE(dev); int i; - DB_PRINT("inited device model\n"); + DB_PRINT("realized spips\n"); s->spi = g_new(SSIBus *, s->num_busses); for (i = 0; i < s->num_busses; ++i) { @@ -531,17 +541,32 @@ static void xilinx_spips_realize(DeviceState *dev, Error **errp) memory_region_init_io(&s->iomem, &spips_ops, s, "spi", R_MAX*4); sysbus_init_mmio(sbd, &s->iomem); - memory_region_init_io(&s->mmlqspi, &lqspi_ops, s, "lqspi", - (1 << LQSPI_ADDRESS_BITS) * 2); - sysbus_init_mmio(sbd, &s->mmlqspi); - s->irqline = -1; - s->lqspi_cached_addr = ~0ULL; fifo8_create(&s->rx_fifo, RXFF_A); fifo8_create(&s->tx_fifo, TXFF_A); } +static void xilinx_qspips_realize(DeviceState *dev, Error **errp) +{ + XilinxSPIPS *s = XILINX_SPIPS(dev); + XilinxQSPIPS *q = XILINX_QSPIPS(dev); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + + DB_PRINT("realized qspips\n"); + + s->num_busses = 2; + s->num_cs = 2; + s->num_txrx_bytes = 4; + + xilinx_spips_realize(dev, errp); + memory_region_init_io(&s->mmlqspi, &lqspi_ops, s, "lqspi", + (1 << LQSPI_ADDRESS_BITS) * 2); + sysbus_init_mmio(sbd, &s->mmlqspi); + + q->lqspi_cached_addr = ~0ULL; +} + static int xilinx_spips_post_load(void *opaque, int version_id) { xilinx_spips_update_ixr((XilinxSPIPS *)opaque); @@ -570,6 +595,14 @@ static Property xilinx_spips_properties[] = { DEFINE_PROP_UINT8("num-txrx-bytes", XilinxSPIPS, num_txrx_bytes, 1), DEFINE_PROP_END_OF_LIST(), }; + +static void xilinx_qspips_class_init(ObjectClass *klass, void * data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->realize = xilinx_qspips_realize; +} + static void xilinx_spips_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -587,9 +620,17 @@ static const TypeInfo xilinx_spips_info = { .class_init = xilinx_spips_class_init, }; +static const TypeInfo xilinx_qspips_info = { + .name = TYPE_XILINX_QSPIPS, + .parent = TYPE_XILINX_SPIPS, + .instance_size = sizeof(XilinxQSPIPS), + .class_init = xilinx_qspips_class_init, +}; + static void xilinx_spips_register_types(void) { type_register_static(&xilinx_spips_info); + type_register_static(&xilinx_qspips_info); } type_init(xilinx_spips_register_types)