From patchwork Thu Apr 18 09:25:39 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kuo-Jung Su X-Patchwork-Id: 237584 X-Patchwork-Delegate: albert.aribaud@free.fr Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 0CDDB2C00BE for ; Thu, 18 Apr 2013 19:29:53 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BD7DD4A34C; Thu, 18 Apr 2013 11:28:02 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 2qt1YP8WyK12; Thu, 18 Apr 2013 11:28:02 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CBD654A377; Thu, 18 Apr 2013 11:27:03 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B2BE94A33E for ; Thu, 18 Apr 2013 11:26:25 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id NNMZe1+12y3u for ; Thu, 18 Apr 2013 11:26:09 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-da0-f46.google.com (mail-da0-f46.google.com [209.85.210.46]) by theia.denx.de (Postfix) with ESMTPS id 68E984A34E for ; Thu, 18 Apr 2013 11:25:48 +0200 (CEST) Received: by mail-da0-f46.google.com with SMTP id y19so1254973dan.33 for ; Thu, 18 Apr 2013 02:25:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:in-reply-to:references; bh=qdu21ey13S+m48hIFsNfDg5KwvoaVAtOFdDEKcxOB4Q=; b=hcW3T0lbJ1uZtQVPfSRzUMEgWQUVwQOB6qJ8Owe41/dwdgSRO1bV5supXnfHGw1J55 PoV+2v8WhrHFxciVLzrni5GpaJ1JBNwmWyqKdw6zS5pbVNxv1Go8QZ/yim3HsEKLXeZV vUyTnv/XryAfGCEKNE6SdQctg69bbEXwhzl+4quj/bN4d2cMDytbOWrYvr0dJMHjjgJf kjJb8Vh4jPf97tE85WmWKYbYbkPeqzJchv4YKbi3PUTLEawhy/PbiZtcd62onJZU69T4 vPpEHvye19ByJOOpCXORBQTaxOwln+ZXzsHr22rbAPIFObHsun556eVR11eld0LAgbzq yEXA== X-Received: by 10.66.102.4 with SMTP id fk4mr2388417pab.167.1366277140655; Thu, 18 Apr 2013 02:25:40 -0700 (PDT) Received: from localhost.localdomain ([220.132.37.35]) by mx.google.com with ESMTPS id xl10sm10280496pac.15.2013.04.18.02.25.38 (version=TLSv1 cipher=DES-CBC3-SHA bits=168/168); Thu, 18 Apr 2013 02:25:39 -0700 (PDT) From: Kuo-Jung Su To: u-boot@lists.denx.de Date: Thu, 18 Apr 2013 17:25:39 +0800 Message-Id: <1366277139-29728-13-git-send-email-dantesu@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1366277139-29728-1-git-send-email-dantesu@gmail.com> References: <1366277139-29728-1-git-send-email-dantesu@gmail.com> In-Reply-To: <1364540788-13943-2-git-send-email-dantesu@gmail.com> References: <1364540788-13943-2-git-send-email-dantesu@gmail.com> Cc: Kuo-Jung Su Subject: [U-Boot] [PATCH v2 12/12] arm: add Faraday A36x SoC platform support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Kuo-Jung Su The Faraday A36x EVB is a Faraday SoC platform evalution board used for Faraday IP functional verification based on the well-known ARM AMBA 2.0 architecture. Faraday A360 EVB: CPU: FA626TE NET: FTMAC110 USB: FUSBH200, FOTG210 LCD: FTLCDC200 I2C: FTI2C010 SPI: FTSSP010 v1.18.0 MMC: FTSDC010 RTC: FTRTC010 WDT: FTWDT010 TMR: FTTMR010 PIC: FTINTC020 UART: FTUART010 NAND: FTNANDC020 Faraday A369 EVB: CPU: FA626TE(Master)/FA606TE(Slave) NET: FTGMAC100 USB: FUSBH200, FOTG210 LCD: FTLCDC200 I2C: FTI2C010 SPI: FTSSP010 v1.18.0 MMC: FTSDC010 RTC: FTRTC011 WDT: FTWDT010 TMR: FTPWMTMR010 PIC: FTINTC020 UART: FTUART010 NAND: FTNANDC021 Signed-off-by: Kuo-Jung Su CC: Albert Aribaud --- arch/arm/cpu/faraday/Makefile | 57 ++++ arch/arm/cpu/faraday/a360/Makefile | 49 +++ arch/arm/cpu/faraday/a360/reset.c | 26 ++ arch/arm/cpu/faraday/a369/Makefile | 50 +++ arch/arm/cpu/faraday/a369/cmd_fa606.c | 75 +++++ arch/arm/cpu/faraday/a369/reset.c | 26 ++ arch/arm/cpu/faraday/cmd_bootfa.c | 132 ++++++++ arch/arm/cpu/faraday/config.mk | 33 ++ arch/arm/cpu/faraday/cpu.c | 238 +++++++++++++ arch/arm/cpu/faraday/ftintc020.h | 37 ++ arch/arm/cpu/faraday/ftpwmtmr010.c | 156 +++++++++ arch/arm/cpu/faraday/ftpwmtmr010.h | 41 +++ arch/arm/cpu/faraday/fttmr010.c | 159 +++++++++ arch/arm/cpu/faraday/fwimage.h | 38 +++ arch/arm/cpu/faraday/fwimage2.h | 70 ++++ arch/arm/cpu/faraday/interrupts.c | 155 +++++++++ arch/arm/cpu/faraday/start.S | 523 +++++++++++++++++++++++++++++ arch/arm/cpu/u-boot.lds | 11 + arch/arm/include/asm/arch-a360/hardware.h | 72 ++++ arch/arm/include/asm/arch-a369/hardware.h | 98 ++++++ arch/arm/include/asm/mach-types.h | 1 + board/faraday/a360evb/Makefile | 49 +++ board/faraday/a360evb/board.c | 67 ++++ board/faraday/a360evb/clk.c | 52 +++ board/faraday/a360evb/config.mk | 33 ++ board/faraday/a360evb/lowlevel_init.S | 33 ++ board/faraday/a369evb/Makefile | 49 +++ board/faraday/a369evb/board.c | 178 ++++++++++ board/faraday/a369evb/clk.c | 81 +++++ board/faraday/a369evb/config.mk | 33 ++ board/faraday/a369evb/lowlevel_init.S | 136 ++++++++ boards.cfg | 3 + include/common.h | 13 + include/configs/a360.h | 185 ++++++++++ include/configs/a369.h | 41 +++ include/configs/a369_defaults.h | 295 ++++++++++++++++ include/configs/a369_fa606te.h | 32 ++ include/faraday/fttmr010.h | 17 + 38 files changed, 3344 insertions(+) create mode 100644 arch/arm/cpu/faraday/Makefile create mode 100644 arch/arm/cpu/faraday/a360/Makefile create mode 100644 arch/arm/cpu/faraday/a360/reset.c create mode 100644 arch/arm/cpu/faraday/a369/Makefile create mode 100644 arch/arm/cpu/faraday/a369/cmd_fa606.c create mode 100644 arch/arm/cpu/faraday/a369/reset.c create mode 100644 arch/arm/cpu/faraday/cmd_bootfa.c create mode 100644 arch/arm/cpu/faraday/config.mk create mode 100644 arch/arm/cpu/faraday/cpu.c create mode 100644 arch/arm/cpu/faraday/ftintc020.h create mode 100644 arch/arm/cpu/faraday/ftpwmtmr010.c create mode 100644 arch/arm/cpu/faraday/ftpwmtmr010.h create mode 100644 arch/arm/cpu/faraday/fttmr010.c create mode 100644 arch/arm/cpu/faraday/fwimage.h create mode 100644 arch/arm/cpu/faraday/fwimage2.h create mode 100644 arch/arm/cpu/faraday/interrupts.c create mode 100644 arch/arm/cpu/faraday/start.S create mode 100644 arch/arm/include/asm/arch-a360/hardware.h create mode 100644 arch/arm/include/asm/arch-a369/hardware.h create mode 100644 board/faraday/a360evb/Makefile create mode 100644 board/faraday/a360evb/board.c create mode 100644 board/faraday/a360evb/clk.c create mode 100644 board/faraday/a360evb/config.mk create mode 100644 board/faraday/a360evb/lowlevel_init.S create mode 100644 board/faraday/a369evb/Makefile create mode 100644 board/faraday/a369evb/board.c create mode 100644 board/faraday/a369evb/clk.c create mode 100644 board/faraday/a369evb/config.mk create mode 100644 board/faraday/a369evb/lowlevel_init.S create mode 100644 include/configs/a360.h create mode 100644 include/configs/a369.h create mode 100644 include/configs/a369_defaults.h create mode 100644 include/configs/a369_fa606te.h -- 1.7.9.5 diff --git a/arch/arm/cpu/faraday/Makefile b/arch/arm/cpu/faraday/Makefile new file mode 100644 index 0000000..fb712a1 --- /dev/null +++ b/arch/arm/cpu/faraday/Makefile @@ -0,0 +1,57 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(CPU).o + +src-y := interrupts.o +src-$(CONFIG_FTPWMTMR010) += ftpwmtmr010.o +src-$(CONFIG_FTTMR010) += fttmr010.o + +START = start.o +COBJS = cpu.o cmd_bootfa.o $(src-y) + +ifdef CONFIG_SPL_BUILD +ifdef CONFIG_SPL_NO_CPU_SUPPORT_CODE +START := +endif +endif + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/arm/cpu/faraday/a360/Makefile b/arch/arm/cpu/faraday/a360/Makefile new file mode 100644 index 0000000..ccd55fa --- /dev/null +++ b/arch/arm/cpu/faraday/a360/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).o + +obj-y := reset.o + +COBJS := $(obj-y) +SOBJS := + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/arm/cpu/faraday/a360/reset.c b/arch/arm/cpu/faraday/a360/reset.c new file mode 100644 index 0000000..ea2db58 --- /dev/null +++ b/arch/arm/cpu/faraday/a360/reset.c @@ -0,0 +1,26 @@ +/* + * arch/arm/cpu/faraday/a360/reset.c + * + * (C) Copyright 2010 Faraday Technology + * Dante Su + * + * This file is released under the terms of GPL v2 and any later version. + * See the file COPYING in the root directory of the source tree for details. + */ + +#include +#include +#include + +#define WDT_READ(r) le32_to_cpu(readl(r)) +#define WDT_WRITE(v, r) writel(cpu_to_le32(v), r) + +void reset_cpu(unsigned long ignored) +{ + struct ftwdt010_wdt *regs = (struct ftwdt010_wdt *)CONFIG_FTWDT010_BASE; + + WDT_WRITE(0, ®s->wdcr); + WDT_WRITE(1000, ®s->wdload); + WDT_WRITE(FTWDT010_WDCR_ENABLE | FTWDT010_WDCR_RST, ®s->wdcr); + WDT_WRITE(FTWDT010_WDRESTART_MAGIC, ®s->wdrestart); +} diff --git a/arch/arm/cpu/faraday/a369/Makefile b/arch/arm/cpu/faraday/a369/Makefile new file mode 100644 index 0000000..5c68d2d --- /dev/null +++ b/arch/arm/cpu/faraday/a369/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).o + +obj-y := reset.o +obj-$(CONFIG_CMD_FA606) += cmd_fa606.o + +COBJS := $(obj-y) +SOBJS := + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/arm/cpu/faraday/a369/cmd_fa606.c b/arch/arm/cpu/faraday/a369/cmd_fa606.c new file mode 100644 index 0000000..3aeca9e --- /dev/null +++ b/arch/arm/cpu/faraday/a369/cmd_fa606.c @@ -0,0 +1,75 @@ +/* + * arch/arm/cpu/faraday/a369/cmd_fa606.c + * + * (C) Copyright 2010 Faraday Technology + * Dante Su + * + * This file is released under the terms of GPL v2 and any later version. + * See the file COPYING in the root directory of the source tree for details. + * + * This command would start the A369 slave cpu - FA606TE, and also immediately + * halt the master cpu - FA626TE. + */ + +#include +#include +#include + +#define SOC_READ(r) le32_to_cpu(readl(r)) +#define SOC_WRITE(v, r) writel(cpu_to_le32(v), r) + +static int do_fa606(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + unsigned int addr = CONFIG_SYS_LOAD_ADDR; + + if (argc >= 2) + addr = simple_strtoul(argv[1], NULL, 16); + + printf("FA606 Image@0x%08X\n", addr); + printf("FA626 is going to enter IDLE state, and never wake-up......\n"); + +#ifndef CONFIG_SYS_DCACHE_OFF + cleanup_before_linux(); +#endif + + /* 1. FA606TE address offset = 0 */ + printf("FA606 address shift disable.\n"); + SOC_WRITE(0x00000000, CONFIG_AHBC2_BASE + 0x90); + + /* 2. Generate a long-jump to 0x00000000 */ + writel(le32_to_cpu(0xEA00000A), 0x00); /* b 0x30 */ + writel(le32_to_cpu(addr), 0x20); + writel(le32_to_cpu(0xE3A00020), 0x30); /* mov r0, #32 ; 0x20 */ + writel(le32_to_cpu(0xE590F000), 0x34); /* ldr pc, [r0] */ + + /* 3. Pinmux = ICE + LCD */ + SOC_WRITE(0x00001078, CONFIG_SCU_BASE + 0x200); + SOC_WRITE(0x26877330, CONFIG_SCU_BASE + 0x228); + SOC_WRITE(0x000A0A0A, CONFIG_SCU_BASE + 0x22c); + SOC_WRITE(0x00003FFF, CONFIG_SCU_BASE + 0x230); + SOC_WRITE(0x00000065, CONFIG_SCU_BASE + 0x238); + SOC_WRITE(0x00000080, CONFIG_SCU_BASE + 0x23c); + udelay(5000); + + /* 4. FA606 clock enable & reset */ + SOC_WRITE(0x00000000, CONFIG_SCU_BASE + 0x028); + udelay(5000); + SOC_WRITE(0x00001878, CONFIG_SCU_BASE + 0x200); + + /* 5. FA626 is going to enter IDLE state, and never wake-up */ + __asm__ __volatile__ ( + "mov r3, #0\n" + "mcr p15,0,r3,c7,c0,4\n" + : + : + : "r3" /* clobber list */ + ); + + return 0; +} + +U_BOOT_CMD( + fa606, 2, 0, do_fa606, + "launch firmware with A369's built-in fa606te\n", + "fa606 [address] - mov pc of fa606te to the specified address.\n" +); diff --git a/arch/arm/cpu/faraday/a369/reset.c b/arch/arm/cpu/faraday/a369/reset.c new file mode 100644 index 0000000..5bb37d5 --- /dev/null +++ b/arch/arm/cpu/faraday/a369/reset.c @@ -0,0 +1,26 @@ +/* + * arch/arm/cpu/faraday/a369/reset.c + * + * (C) Copyright 2010 Faraday Technology + * Dante Su + * + * This file is released under the terms of GPL v2 and any later version. + * See the file COPYING in the root directory of the source tree for details. + */ + +#include +#include +#include + +#define WDT_READ(r) le32_to_cpu(readl(r)) +#define WDT_WRITE(v, r) writel(cpu_to_le32(v), r) + +void reset_cpu(unsigned long ignored) +{ + struct ftwdt010_wdt *regs = (struct ftwdt010_wdt *)CONFIG_FTWDT010_BASE; + + WDT_WRITE(0, ®s->wdcr); + WDT_WRITE(1000, ®s->wdload); + WDT_WRITE(FTWDT010_WDCR_ENABLE | FTWDT010_WDCR_RST, ®s->wdcr); + WDT_WRITE(FTWDT010_WDRESTART_MAGIC, ®s->wdrestart); +} diff --git a/arch/arm/cpu/faraday/cmd_bootfa.c b/arch/arm/cpu/faraday/cmd_bootfa.c new file mode 100644 index 0000000..bcced38 --- /dev/null +++ b/arch/arm/cpu/faraday/cmd_bootfa.c @@ -0,0 +1,132 @@ +/* + * arch/arm/cpu/faraday/cmd_bootfa.c + * + * (C) Copyright 2010 Faraday Technology + * Dante Su + * + * This file is released under the terms of GPL v2 and any later version. + * See the file COPYING in the root directory of the source tree for details. + * + * This command would try to boot faraday image from MMC/SD/USB/SPI/NAND/NOR + */ + +#include +#include + +#include "fwimage2.h" + +#undef ROUNDUP +#define ROUNDUP(len, blksz) \ + ((len) % (blksz)) ? ((len) + (blksz) - ((len) % (blksz))) : (len) + +static struct fwpart *part_lookup(struct fwimage2 *hdr, char *name) +{ + int i; + struct fwpart *part = hdr->part; + + for (i = 0; part[i].length > 0 && i < 10; ++i) { + if (strcmp(name, part[i].name) == 0) { + printf("part_lookup: name=%s, offset=0x%x, size=0x%x\n", + part[i].name, part[i].offset, part[i].length); + return part + i; + } + } + + return NULL; +} + +static int do_bootfa(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + char *inf, *name , cmd[256]; + struct fwpart *part; + + if (argc < 3) { +#ifdef CONFIG_SYS_LONGHELP + printf("Usage:\n" + "%s %s\n", argv[0], cmdtp->help); +#else + printf("Usage:\n" + "bootfa \n" + " - boot from 'interface' with the firmware named as \n" + " where 'interface' could be any one of \n" + "ex: bootfa usb linux"); +#endif + return 1; + } + + inf = argv[1]; + name = argv[2]; + + if (!strcmp(inf, "usb")) { + if (!strcmp(name, "linux")) + name = "zimage"; + else if (!strcmp(name, "wince")) + name = "nk.nb0"; + sprintf(cmd, "usb start;fatload usb 0 0x%x %s", + CONFIG_SYS_LOAD_ADDR, name); + run_command(cmd, 0); + } else if (!strcmp(inf, "mmc") || !strcmp(inf, "sd")) { + if (!strcmp(name, "linux")) + name = "zimage"; + else if (!strcmp(name, "wince")) + name = "nk.nb0"; + sprintf(cmd, "mmcinfo;fatload mmc 0 0x%x %s", + CONFIG_SYS_LOAD_ADDR, name); + run_command(cmd, 0); +#ifdef CONFIG_SYS_FLASH_BASE + } else if (!strcmp(inf, "nor")) { + sprintf(cmd, "cp.l 0x%x 0x%x 0x400", + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_LOAD_ADDR); + run_command(cmd, 0); + part = part_lookup((void *)CONFIG_SYS_LOAD_ADDR, name); + if (!part) { + printf("firmware not found!\n"); + return 1; + } + sprintf(cmd, "cp.l 0x%x 0x%x 0x%x", + CONFIG_SYS_FLASH_BASE + part->offset, + CONFIG_SYS_LOAD_ADDR, part->length); + run_command(cmd, 0); +#endif + } else if (!strcmp(inf, "nand")) { + sprintf(cmd, "nand read 0x%x 0 0x400", CONFIG_SYS_LOAD_ADDR); + run_command(cmd, 0); + part = part_lookup((void *)CONFIG_SYS_LOAD_ADDR, name); + if (!part) { + printf("firmware not found!\n"); + return 1; + } + sprintf(cmd, "nand read 0x%x 0x%x 0x%x", + CONFIG_SYS_LOAD_ADDR, + part->offset, part->length); + run_command(cmd, 0); + } else if (!strcmp(inf, "sf")) { + sprintf(cmd, "sf probe 0:0 25000000;sf read 0x%x 0 0x400", + CONFIG_SYS_LOAD_ADDR); + run_command(cmd, 0); + part = part_lookup((void *)CONFIG_SYS_LOAD_ADDR, name); + if (!part) { + printf("firmware not found!\n"); + return 1; + } + sprintf(cmd, "sf read 0x%x 0x%x 0x%x", + CONFIG_SYS_LOAD_ADDR, + part->offset, part->length); + run_command(cmd, 0); + } + + sprintf(cmd, "go 0x%x", CONFIG_SYS_LOAD_ADDR); + run_command(cmd, 0); + + return 1; +} + +U_BOOT_CMD( + bootfa, 3, 1, do_bootfa, + "boot faraday firmware image", + " \n" + " - boot from 'interface' with the firmware named as \n" + " where 'interface' could be any one of \n" + "ex: bootfa usb linux" +); diff --git a/arch/arm/cpu/faraday/config.mk b/arch/arm/cpu/faraday/config.mk new file mode 100644 index 0000000..ffb2e6c --- /dev/null +++ b/arch/arm/cpu/faraday/config.mk @@ -0,0 +1,33 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float + +PLATFORM_CPPFLAGS += -march=armv5te +# ========================================================================= +# +# Supply options according to compiler version +# +# ========================================================================= +PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) +PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) diff --git a/arch/arm/cpu/faraday/cpu.c b/arch/arm/cpu/faraday/cpu.c new file mode 100644 index 0000000..56c4d72 --- /dev/null +++ b/arch/arm/cpu/faraday/cpu.c @@ -0,0 +1,238 @@ +/* + * arch/arm/cpu/faraday/cpu.c + * + * (C) Copyright 2010 Faraday Technology + * Dante Su + * + * This file is released under the terms of GPL v2 and any later version. + * See the file COPYING in the root directory of the source tree for details. + */ + +/* + * CPU specific code + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int cleanup_before_linux(void) +{ + /* + * this function is called just before we call linux + * it prepares the processor for linux + * + * we turn off caches etc ... + */ + + disable_interrupts(); + + /* turn off D-cache */ + dcache_disable(); + + /* flush I-cache */ + __asm__ __volatile__ ( + "mov r3, #0\n" + "mcr p15, 0, r3, c7, c5, 0\n" /* invalidate i-cache all */ + : /* output */ + : /* input */ + : "r3" /* clobber list */ + ); + + return 0; +} + +void arch_preboot_os(void) +{ + cleanup_before_linux(); +} + +#ifdef CONFIG_SYS_DCACHE_OFF + +void flush_dcache_range(unsigned long start, unsigned long stop) +{ +} + +void invalidate_dcache_range(unsigned long start, unsigned long stop) +{ +} + +#else + +void flush_dcache_all(void) +{ + __asm__ __volatile__ ( + "mov r3,#0\n" + "mcr p15,0,r3,c7,c14,0\n" /* clean & invalidate d-cache all */ + "mcr p15,0,r3,c7,c10,4\n" /* drain write buffer */ + : /* output */ + : /* input */ + : "r3" /* clobber list */ + ); +} + +void flush_dcache_range(unsigned long start, unsigned long stop) +{ + unsigned long align = CONFIG_SYS_CACHELINE_SIZE; + unsigned long mask = ~(align - 1); + + /* aligned to cache line */ + stop = (stop + (align - 1)) & mask; + start = start & mask; + + __asm__ __volatile__ ( + "1:\n" + "mcr p15,0,%0,c7,c14,1\n" /* clean & invalidate d-cache line */ + "add %0,%0,%2\n" + "cmp %0,%1\n" + "blo 1b\n" + "mov r3,#0\n" + "mcr p15,0,r3,c7,c10,4\n" /* drain write buffer */ + : "+r"(start) /* output */ + : "r"(stop), "r"(align) /* input */ + : "r3" /* clobber list */ + ); +} + +void invalidate_dcache_range(unsigned long start, unsigned long stop) +{ + unsigned long align = CONFIG_SYS_CACHELINE_SIZE; + unsigned long mask = ~(align - 1); + + /* aligned to cache line */ + stop = (stop + (align - 1)) & mask; + start = start & mask; + + __asm__ __volatile__ ( + "1:\n" + "mcr p15,0,%0,c7,c6,1\n" /* invalidate cache line */ + "add %0,%0,%2\n" + "cmp %0,%1\n" + "blo 1b\n" + : "+r"(start) /* output */ + : "r"(stop), "r"(align) /* input */ + ); +} + +void invalidate_dcache_all(void) +{ + __asm__ __volatile__ ( + "mov r3,#0\n" + "mcr p15,0,r3,c7,c6,0\n" /* invalidate d-cache all */ + : /* output */ + : /* input */ + : "r3" /* clobber list */ + ); +} + +void invalidate_icache_all(void) +{ + __asm__ __volatile__ ( + "mov r3,#0\n" + "mcr p15,0,r3,c7,c5,0\n" /* invalidate i-cache all */ + : /* output */ + : /* input */ + : "r3" /* clobber list */ + ); +} + +void flush_cache(unsigned long start, unsigned long size) +{ + flush_dcache_range(start, start + size); +} + +#endif /* !defined(CONFIG_SYS_DCACHE_OFF) */ + +void enable_caches(void) +{ + icache_enable(); + +#if !defined(CONFIG_SYS_DCACHE_OFF) + if (gd->arch.cpu_mmu) { + puts("MMU: on\n"); + dcache_enable(); + } else +#endif + puts("MMU: off\n"); +} + +#ifdef CONFIG_ARCH_CPU_INIT + +int arch_cpu_init(void) +{ + unsigned int id, ctr; + + __asm__ __volatile__ ( + "mrc p15, 0, %0, c0, c0, 0\n" + "mrc p15, 0, %1, c0, c0, 1\n" + : "=r"(id), "=r"(ctr) /* output */ + : /* input */ + ); + + gd->arch.cpu_id = id; + + /* MMU/D-Cache */ + switch (gd->arch.cpu_id >> 4) { + case 0x6604526: /* FA526 */ + case 0x6604626: /* FA626 */ + case 0x6605606: /* FA606TE */ + /* Disable MMU/D-Cache */ + gd->arch.cpu_mmu = 0; + break; + default: + /* Enable MMU/D-Cache */ + gd->arch.cpu_mmu = 1; + break; + } + + return 0; +} +#endif /* #ifdef CONFIG_ARCH_CPU_INIT */ + +#ifdef CONFIG_DISPLAY_CPUINFO +int print_cpuinfo(void) +{ + char cpu_name[32]; + uint vid = gd->arch.cpu_id >> 24; + uint pid = (gd->arch.cpu_id & 0xfff0) >> 4; + + /* build cpu_name */ + switch (vid) { + case 0x66: /* Faraday */ + switch (gd->arch.cpu_id >> 16) { + case 0x6601: + sprintf(cpu_name, "FA%x", pid); + break; + default: + sprintf(cpu_name, "FA%xTE", pid); + break; + } + break; + case 0x41: /* ARM */ + if ((pid & 0xff0) == 0xc00) + sprintf(cpu_name, "Cortex-A%u", (pid & 0x00f)); + else if (pid >= 0xa00) + sprintf(cpu_name, "ARM%x", 0x1000 + (pid - 0xa00)); + else + sprintf(cpu_name, "ARM%x", pid); + break; + default: + sprintf(cpu_name, "Unknown"); + break; + } + + /* print cpu_info */ + printf("CPU: %s %u MHz\n", + cpu_name, (unsigned int)(clk_get_rate("CPU") / 1000000)); + + printf("AHB: %u MHz\n", + (unsigned int)(clk_get_rate("AHB") / 1000000)); + + printf("APB: %u MHz\n", + (unsigned int)(clk_get_rate("APB") / 1000000)); + + return 0; +} +#endif /* #ifdef CONFIG_DISPLAY_CPUINFO */ diff --git a/arch/arm/cpu/faraday/ftintc020.h b/arch/arm/cpu/faraday/ftintc020.h new file mode 100644 index 0000000..e23d1e7 --- /dev/null +++ b/arch/arm/cpu/faraday/ftintc020.h @@ -0,0 +1,37 @@ +/* + * arch/arm/cpu/faraday/ftintc020.h + * + * (C) Copyright 2010 Faraday Technology + * Dante Su + * + * This file is released under the terms of GPL v2 and any later version. + * See the file COPYING in the root directory of the source tree for details. + */ + +#ifndef ARCH_ARM_CPU_FARADAY_FTINTC020_H +#define ARCH_ARM_CPU_FARADAY_FTINTC020_H + +struct ftintc020_pic_regs { + uint32_t src; /* source register */ + uint32_t ena; /* enable register */ + uint32_t scr; /* status clear register */ + uint32_t tmr; /* trigger mode register */ + uint32_t tlr; /* trigger level register */ + uint32_t sr; /* status register */ + uint32_t rsvd[2]; +}; + +struct ftintc020_regs { + /* IRQ/FIQ: 0 ~ 31 */ + struct ftintc020_pic_regs irq32; /* 0x00 - 0x1C: IRQ 0 ~ 31 */ + struct ftintc020_pic_regs fiq32; /* 0x20 - 0x3C: FIQ 0 ~ 31 */ + uint32_t rsvd1[4]; /* 0x40 - 0x4C: Reserved */ + uint32_t revision; /* 0x50: Revision Register */ + uint32_t feature; /* 0x54: Feature Register */ + uint32_t rsvd2[2]; /* 0x58 - 0x5C: Reserved */ + /* IRQ/FIQ: 32 ~ 63 */ + struct ftintc020_pic_regs irq64; /* 0x60 - 0x7C: IRQ 32 ~ 63 */ + struct ftintc020_pic_regs fiq64; /* 0x80 - 0x9C: FIQ 32 ~ 63 */ +}; + +#endif diff --git a/arch/arm/cpu/faraday/ftpwmtmr010.c b/arch/arm/cpu/faraday/ftpwmtmr010.c new file mode 100644 index 0000000..39d5ba1 --- /dev/null +++ b/arch/arm/cpu/faraday/ftpwmtmr010.c @@ -0,0 +1,156 @@ +/* + * arch/arm/cpu/faraday/ftpwmtmr010.c + * + * (C) Copyright 2010 Faraday Technology + * Dante Su + * + * This file is released under the terms of GPL v2 and any later version. + * See the file COPYING in the root directory of the source tree for details. + */ + +#include +#include + +#include "ftpwmtmr010.h" + +#ifdef CONFIG_A369_FA606TE_PLATFORM +#define TIMER_ID 4 +#else +#define TIMER_ID 0 +#endif + +#define TMR_READ(r) le32_to_cpu(readl(r)) +#define TMR_WRITE(v, r) writel(cpu_to_le32(v), r) + +static ulong ticks; /* U-Boot ticks since startup */ +static ulong sclk = 66000000; /* source clock (66MHz by default) */ +static struct ftpwmtmr010_regs *regs = (void *)CONFIG_TIMER_BASE; + +void udelay_masked(unsigned long usec) +{ + int id = TIMER_ID + 1; + + /* timer re-start */ + TMR_WRITE(0, ®s->t[id].ctrl); + TMR_WRITE(BIT_MASK(id), ®s->isr); + TMR_WRITE(0, ®s->t[id].cmpb); + TMR_WRITE((sclk / 1000000) * usec, ®s->t[id].cntb); + TMR_WRITE(CTRL_INTEN | CTRL_START | CTRL_UPDATE, ®s->t[id].ctrl); + + /* wait for timer interrupt */ + while (!(TMR_READ(®s->isr) & BIT_MASK(id))) + ; + + /* timer disabled */ + TMR_WRITE(0, ®s->t[id].ctrl); + TMR_WRITE(BIT_MASK(id), ®s->isr); +} + +#ifdef CONFIG_USE_IRQ + +void timer_interrupt(struct pt_regs *ctx) +{ + int id = TIMER_ID; + ++ticks; + TMR_WRITE(BIT_MASK(id), ®s->isr); +} + +#endif /* #ifdef CONFIG_USE_IRQ */ + +void reset_timer_masked(void) +{ + int id = TIMER_ID; + + TMR_WRITE(0, ®s->t[id].ctrl); + TMR_WRITE(BIT_MASK(id), ®s->isr); + +#ifdef CONFIG_USE_IRQ + /* setup a 1 sec periodic timer */ + TMR_WRITE(0, + ®s->t[id].cmpb); + TMR_WRITE(sclk / CONFIG_SYS_HZ, + ®s->t[id].cntb); + TMR_WRITE(CTRL_AUTORELOAD | CTRL_INTEN | CTRL_START | CTRL_UPDATE, + ®s->t[id].ctrl); + irq_install_handler(CONFIG_TIMER_IRQ, (void *)timer_interrupt, NULL); + irq_enable(CONFIG_TIMER_IRQ); + enable_interrupts(); +#else + /* setup a 30 sec one-shot timer */ + TMR_WRITE(0, + ®s->t[id].cmpb); + TMR_WRITE(30 * sclk, + ®s->t[id].cntb); + TMR_WRITE(CTRL_INTEN | CTRL_START | CTRL_UPDATE, + ®s->t[id].ctrl); +#endif /* #ifdef CONFIG_USE_IRQ */ +} + +ulong get_timer_masked(void) +{ +#ifdef CONFIG_USE_IRQ + return ticks; +#else + ulong s = sclk / CONFIG_SYS_HZ; + ulong t = (30 * sclk - TMR_READ(®s->t[TIMER_ID].cnto)) / s; + return ticks + t; +#endif +} + +int timer_init(void) +{ + ticks = 0; + sclk = clk_get_rate("APB"); + +#ifdef CONFIG_USE_IRQ + /* interrupt is not yet initialized here */ +#else + reset_timer_masked(); +#endif + + return 0; +} + +void reset_timer(void) +{ + reset_timer_masked(); +} + +ulong get_timer(ulong base) +{ +#ifndef CONFIG_USE_IRQ + if (!TMR_READ(®s->t[TIMER_ID].cnto)) { + ticks += 30 * CONFIG_SYS_HZ; + reset_timer_masked(); + } +#endif + return get_timer_masked() - base; +} + +void set_timer(ulong t) +{ + ticks = t; +} + +void __udelay(unsigned long usec) +{ + udelay_masked(usec); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + return CONFIG_SYS_HZ; +} diff --git a/arch/arm/cpu/faraday/ftpwmtmr010.h b/arch/arm/cpu/faraday/ftpwmtmr010.h new file mode 100644 index 0000000..9455577 --- /dev/null +++ b/arch/arm/cpu/faraday/ftpwmtmr010.h @@ -0,0 +1,41 @@ +/* + * arch/arm/cpu/faraday/ftpwmtmr010.h + * + * (C) Copyright 2010 Faraday Technology + * Dante Su + * + * This file is released under the terms of GPL v2 and any later version. + * See the file COPYING in the root directory of the source tree for details. + */ + +#ifndef ARCH_ARM_CPU_FARADAY_FTPWMTMR010_H +#define ARCH_ARM_CPU_FARADAY_FTPWMTMR010_H + +struct ftpwmtmr010_timer { + uint32_t ctrl; /* Control */ +#define CTRL_EXTCLK (1 << 0) /* use external clock */ +#define CTRL_START (1 << 1) /* timer start */ +#define CTRL_UPDATE (1 << 2) /* update timer counter */ +#define CTRL_AUTORELOAD (1 << 4) /* auto-reload timer counter */ +#define CTRL_INTEN (1 << 5) /* interrupt enabled */ + + uint32_t cntb; /* Count buffer */ + uint32_t cmpb; /* Compare buffer */ + uint32_t cnto; /* Count observation */ +}; + +struct ftpwmtmr010_regs { + /* 0x00: Interrupt status register */ + uint32_t isr; + + /* 0x04 - 0x0C: Reserved */ + uint32_t rsvd[3]; + + /* 0x10 - 0x8C: timer registers */ + struct ftpwmtmr010_timer t[8]; + + /* 0x90: Revision register */ + uint32_t rev; +}; + +#endif diff --git a/arch/arm/cpu/faraday/fttmr010.c b/arch/arm/cpu/faraday/fttmr010.c new file mode 100644 index 0000000..e8f1a2c --- /dev/null +++ b/arch/arm/cpu/faraday/fttmr010.c @@ -0,0 +1,159 @@ +/* + * arch/arm/cpu/faraday/fttmr010.c + * + * (C) Copyright 2010 Faraday Technology + * Dante Su + * + * This file is released under the terms of GPL v2 and any later version. + * See the file COPYING in the root directory of the source tree for details. + */ + +#include +#include +#include + +#define TMR_READ(r) le32_to_cpu(readl(r)) +#define TMR_WRITE(v, r) writel(cpu_to_le32(v), r) +#define TMR_SETBITS(m, r) setbits_le32(r, m) +#define TMR_CLRBITS(m, r) clrbits_le32(r, m) + +static ulong ticks; /* U-Boot ticks since startup */ +static ulong sclk = 66000000; /* source clock (66MHz by default) */ +static struct fttmr010 *regs = (void *)CONFIG_TIMER_BASE; + +void udelay_masked(unsigned long usec) +{ + /* Disable Timer2 */ + TMR_CLRBITS(FTTMR010_TM2_CRMASK, ®s->cr); + /* Disable Timer2 interrupts */ + TMR_WRITE(FTTMR010_TM2_ISRMASK, ®s->interrupt_mask); + /* Clear Timer2 interrupts */ + TMR_WRITE(FTTMR010_TM2_ISRMASK, ®s->interrupt_state); + + /* Configure Timer2 */ + TMR_WRITE((sclk / 1000000) * usec, ®s->timer2_counter); + TMR_WRITE(0, ®s->timer2_load); + TMR_WRITE(0, ®s->timer2_match1); + TMR_WRITE(0, ®s->timer2_match2); + + /* Enable Timer2 */ + TMR_SETBITS(FTTMR010_TM2_OFENABLE | FTTMR010_TM2_ENABLE, ®s->cr); + + /* Wait until timeout */ + while (!(TMR_READ(®s->interrupt_state) & FTTMR010_TM2_ISRMASK)) + ; +} + +#ifdef CONFIG_USE_IRQ + +void timer_interrupt(struct pt_regs *ctx) +{ + ++ticks; + TMR_WRITE(FTTMR010_TM1_ISRMASK, ®s->interrupt_state); +} + +#endif /* #ifdef CONFIG_USE_IRQ */ + +void reset_timer_masked(void) +{ + /* Disable Timer1 */ + TMR_CLRBITS(FTTMR010_TM1_CRMASK, ®s->cr); + /* Disable Timer1 interrupts */ + TMR_WRITE(FTTMR010_TM1_ISRMASK, ®s->interrupt_mask); + /* Clear Timer1 interrupts */ + TMR_WRITE(FTTMR010_TM1_ISRMASK, ®s->interrupt_state); + +#ifdef CONFIG_USE_IRQ + /* interrupt init */ + irq_set_trigger(CONFIG_TIMER_IRQ, 1, 0); + irq_install_handler(CONFIG_TIMER_IRQ, (void *)timer_interrupt, NULL); + irq_enable(CONFIG_TIMER_IRQ); +#endif + + /* timer1 setup */ +#ifdef CONFIG_USE_IRQ + /* setup a 1 sec periodic timer */ + TMR_WRITE(sclk / CONFIG_SYS_HZ, ®s->timer1_counter); + TMR_WRITE(sclk / CONFIG_SYS_HZ, ®s->timer1_load); +#else + /* setup a 30 sec one-shot timer */ + TMR_WRITE(30 * sclk, ®s->timer1_counter); + TMR_WRITE(0, ®s->timer1_load); +#endif + TMR_WRITE(0, ®s->timer1_match1); + TMR_WRITE(0, ®s->timer1_match2); + + /* start timer1 with overflow interrupt enabled */ + TMR_WRITE(FTTMR010_TM1_MATCH1 | FTTMR010_TM1_MATCH2, + ®s->interrupt_mask); + TMR_SETBITS(FTTMR010_TM1_OFENABLE | FTTMR010_TM1_ENABLE, + ®s->cr); +} + +ulong get_timer_masked(void) +{ +#ifdef CONFIG_USE_IRQ + return ticks; +#else + ulong s = sclk / CONFIG_SYS_HZ; + ulong t = ((30 * sclk) - TMR_READ(®s->timer1_counter)) / s; + return ticks + t; +#endif +} + +int timer_init(void) +{ + ticks = 0; + sclk = clk_get_rate("APB"); + +#ifdef CONFIG_USE_IRQ + /* interrupt is not yet initialized here */ +#else + reset_timer_masked(); +#endif + return 0; +} + +void reset_timer(void) +{ + reset_timer_masked(); +} + +ulong get_timer(ulong base) +{ +#ifndef CONFIG_USE_IRQ + if (!TMR_READ(®s->timer1_counter)) { + ticks += 30 * CONFIG_SYS_HZ; + reset_timer_masked(); + } +#endif + return get_timer_masked() - base; +} + +void set_timer(ulong t) +{ + ticks = t; +} + +void __udelay(unsigned long usec) +{ + udelay_masked(usec); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + return CONFIG_SYS_HZ; +} diff --git a/arch/arm/cpu/faraday/fwimage.h b/arch/arm/cpu/faraday/fwimage.h new file mode 100644 index 0000000..af4f2f9 --- /dev/null +++ b/arch/arm/cpu/faraday/fwimage.h @@ -0,0 +1,38 @@ +/* + * arch/arm/cpu/faraday/fwimage.h + * + * (C) Copyright 2010 Faraday Technology + * Dante Su + * + * This file is released under the terms of GPL v2 and any later version. + * See the file COPYING in the root directory of the source tree for details. + */ + +#ifndef ARCH_ARM_CPU_FARADAY_FWIMAGE_H +#define ARCH_ARM_CPU_FARADAY_FWIMAGE_H + +struct fwparam { + uint32_t count; + uint32_t version; /* ycmo100525: for firmware image version */ + uint32_t addr[31]; + uint32_t data[31]; +}; + +struct fwfile { + char name[64]; + uint32_t size; + /* uint32_t block[1]; */ +}; + +struct fwimage { + /* 8 bytes */ + uint32_t magic; /* Magic number */ + uint32_t length; /* It shall not be greater than 2048 */ + + /* 256 bytes, embedded paramters area */ + struct fwparam param; + + struct fwfile file[1]; +}; + +#endif diff --git a/arch/arm/cpu/faraday/fwimage2.h b/arch/arm/cpu/faraday/fwimage2.h new file mode 100644 index 0000000..27319a7 --- /dev/null +++ b/arch/arm/cpu/faraday/fwimage2.h @@ -0,0 +1,70 @@ +/* + * arch/arm/cpu/faraday/fwimage2.h + * + * (C) Copyright 2010 Faraday Technology + * Dante Su + * + * This file is released under the terms of GPL v2 and any later version. + * See the file COPYING in the root directory of the source tree for details. + */ + +#ifndef ARCH_ARM_CPU_FARADAY_FWIMAGE2_H +#define ARCH_ARM_CPU_FARADAY_FWIMAGE2_H + +#include +#include "fwimage.h" + +/* 8 bytes struct for generic 32-bit memory write */ +struct fwmw32 { + uint32_t addr; + uint32_t data; +}; + +/* 72 bytes */ +struct fwpart { + /* offset: 0 ~ 63 */ + char name[32]; + + uint32_t offset; + uint32_t length; + + uint32_t load; + uint32_t qcrc; /* Quick CRC32 against 256KB on both TOP & BOTTOM */ + + uint32_t flag; +#define FWIMAGE2_FLAG_UIMAGE 0x00000001 /* Is a uImage ? */ +#define FWIMAGE2_FLAG_FILESYSTEM 0x00000010 /* Is a filesystem ? */ + + uint8_t rsvd[12]; + + /* offset: 64 ~ 71 */ + uint32_t magic1000; /* It's always 0x00001000 */ + uint32_t magic0001; /* It's always 0x00000001 */ +}; + +struct fwimage2 { + /* 4 bytes, magic */ + uint32_t magic; /* Image Header Magic Number */ +#define FWIMAGE2_MAGIC 0x00484946 /* "FIH\0" */ + + /* 4 bytes, header length */ + uint32_t hlen; /* Image Header Length */ + + /* 256 bytes, embedded paramters area */ + struct fwmw32 mw32[32]; + + /* 720 bytes, firmware partition table */ + struct fwpart part[10]; + + /* 4 bytes */ + uint32_t hcrc; /* Image Header Checksum (CRC32) */ + + /* 4 bytes, revision */ + uint32_t revision; /* Image Header Revision Code */ +#define FWIMAGE2_REVISION 0x00000201 /* v2.1 */ + + /* 32 bytes */ + char build[32]; /* Build Date (yyyy/mm/dd HH:MM:SS) */ +}; /* Total 1024 bytes */ + +#endif diff --git a/arch/arm/cpu/faraday/interrupts.c b/arch/arm/cpu/faraday/interrupts.c new file mode 100644 index 0000000..162c454 --- /dev/null +++ b/arch/arm/cpu/faraday/interrupts.c @@ -0,0 +1,155 @@ +/* + * arch/arm/cpu/faraday/interrupts.c + * + * (C) Copyright 2010 Faraday Technology + * Dante Su + * + * This file is released under the terms of GPL v2 and any later version. + * See the file COPYING in the root directory of the source tree for details. + */ + +#include +#include + +#include "ftintc020.h" + +#ifdef CONFIG_USE_IRQ + +#define PIC_READ(r) le32_to_cpu(readl(r)) +#define PIC_WRITE(v, r) writel(cpu_to_le32(v), r) +#define PIC_SETBITS(m, r) setbits_le32(r, m) +#define PIC_CLRBITS(m, r) clrbits_le32(r, m) + +static struct ftintc020_regs *regs = (void *)CONFIG_PIC_BASE; + +struct _irq_handler { + void *data; + void (*func)(void *data); +}; + +static struct _irq_handler IRQ_HANDLER[64]; + +static inline void irq_acknowledge(int irq) +{ + uint32_t mask = BIT_MASK(irq); + + if (irq < 32) + PIC_WRITE(mask, ®s->irq32.scr); + else + PIC_WRITE(mask, ®s->irq64.scr); +} + +void irq_enable(int irq) +{ + uint32_t mask = BIT_MASK(irq); + + if (irq < 32) + PIC_SETBITS(mask, ®s->irq32.ena); + else + PIC_SETBITS(mask, ®s->irq64.ena); +} + +void irq_disable(int irq) +{ + uint32_t mask = BIT_MASK(irq); + + if (irq < 32) + PIC_CLRBITS(mask, ®s->irq32.ena); + else + PIC_CLRBITS(mask, ®s->irq64.ena); +} + +void irq_set_trigger(int irq, int edge, int low) +{ + uint32_t mask = BIT_MASK(irq); + + if (edge) { + if (irq < 32) + PIC_SETBITS(mask, ®s->irq32.tmr); + else + PIC_SETBITS(mask, ®s->irq64.tmr); + } else { + if (irq < 32) + PIC_CLRBITS(mask, ®s->irq32.tmr); + else + PIC_CLRBITS(mask, ®s->irq64.tmr); + } + + if (low) { + if (irq < 32) + PIC_SETBITS(mask, ®s->irq32.tlr); + else + PIC_SETBITS(mask, ®s->irq64.tlr); + } else { + if (irq < 32) + PIC_CLRBITS(mask, ®s->irq32.tlr); + else + PIC_CLRBITS(mask, ®s->irq64.tlr); + } +} + +void do_irq(struct pt_regs *pt_regs) +{ + int irq; + uint32_t stat; + + irq = 32; + stat = PIC_READ(®s->irq64.sr); /* IRQ 32 ~ 63 */ + if (!stat) { + irq = 0; + stat = PIC_READ(®s->irq32.sr); /* IRQ 0 ~ 31 */ + } + irq += ffs(stat) - 1; + + if (irq < 0) { + printf("interrupts: no irq!?\n"); + } else { + irq_acknowledge(irq); + IRQ_HANDLER[irq].func(IRQ_HANDLER[irq].data); + } +} + +static void default_isr(void *data) +{ + printf("default_isr(): called for IRQ %d\n", (int)data); +} + +void irq_install_handler(int irq, interrupt_handler_t *hndl, void *data) +{ + if (irq >= 0 && irq < 64) { + IRQ_HANDLER[irq].func = hndl; + IRQ_HANDLER[irq].data = data; + } +} + +void irq_free_handler(int irq) +{ + if (irq >= 0 && irq < 64) { + IRQ_HANDLER[irq].func = default_isr; + IRQ_HANDLER[irq].data = (void *)irq; + irq_disable(irq); + } +} + +int arch_interrupt_init(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(IRQ_HANDLER); ++i) + irq_free_handler(i); + + /* hardware reset */ + PIC_WRITE(0x00000000, ®s->irq32.ena); + PIC_WRITE(0xffffffff, ®s->irq32.scr); + PIC_WRITE(0x00000000, ®s->irq32.tmr); + PIC_WRITE(0x00000000, ®s->irq32.tlr); + + PIC_WRITE(0x00000000, ®s->irq64.ena); + PIC_WRITE(0xffffffff, ®s->irq64.scr); + PIC_WRITE(0x00000000, ®s->irq64.tmr); + PIC_WRITE(0x00000000, ®s->irq64.tlr); + + return 0; +} + +#endif /* #ifdef CONFIG_USE_IRQ */ diff --git a/arch/arm/cpu/faraday/start.S b/arch/arm/cpu/faraday/start.S new file mode 100644 index 0000000..2d5e1cd --- /dev/null +++ b/arch/arm/cpu/faraday/start.S @@ -0,0 +1,523 @@ +/* + * u-boot - Startup Code for Faraday CPU-core + * + * Base is arch/arm/cpu/arm926ejs/start.S + * + * (C) Copyright 2010 Faraday Technology + * Dante Su + * + * This file is released under the terms of GPL v2 and any later version. + * See the file COPYING in the root directory of the source tree for details. + */ + +#include +#include +#include +#include + +/* + ************************************************************************* + * + * Jump vector table as in table 3.1 in [1] + * + ************************************************************************* + */ + + +#ifdef CONFIG_SYS_DV_NOR_BOOT_CFG +.globl _start +_start: +.globl _NOR_BOOT_CFG +_NOR_BOOT_CFG: + .word CONFIG_SYS_DV_NOR_BOOT_CFG + b reset +#else +.globl _start +_start: + b reset +#endif +#ifdef CONFIG_SPL_BUILD +/* No exception handlers in preloader */ + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + +_hang: + .word do_hang +/* pad to 64 byte boundary */ + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 +#else + ldr pc, _undefined_instruction + ldr pc, _software_interrupt + ldr pc, _prefetch_abort + ldr pc, _data_abort + ldr pc, _not_used + ldr pc, _irq + ldr pc, _fiq + +_undefined_instruction: + .word undefined_instruction +_software_interrupt: + .word software_interrupt +_prefetch_abort: + .word prefetch_abort +_data_abort: + .word data_abort +_not_used: + .word not_used +_irq: + .word irq +_fiq: + .word fiq + +#endif /* CONFIG_SPL_BUILD */ + .balignl 16,0xdeadbeef + + +/* + ************************************************************************* + * + * Startup Code (reset vector) + * + * do important init only if we don't start from memory! + * setup Memory and board specific bits prior to relocation. + * relocate armboot to ram + * setup stack + * + ************************************************************************* + */ + +.globl _TEXT_BASE +_TEXT_BASE: +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) + .word CONFIG_SPL_TEXT_BASE +#else + .word CONFIG_SYS_TEXT_BASE +#endif + +/* + * These are defined in the board-specific linker script. + * Subtracting _start from them lets the linker put their + * relative position in the executable instead of leaving + * them null. + */ +.globl _bss_start_ofs +_bss_start_ofs: + .word __bss_start - _start + +.globl _image_copy_end_ofs +_image_copy_end_ofs: + .word __image_copy_end - _start + +.globl _bss_end_ofs +_bss_end_ofs: + .word __bss_end - _start + +.globl _end_ofs +_end_ofs: + .word _end - _start + +#ifdef CONFIG_USE_IRQ +/* IRQ stack memory (calculated at run-time) */ +.globl IRQ_STACK_START +IRQ_STACK_START: + .word 0x0badc0de + +/* IRQ stack memory (calculated at run-time) */ +.globl FIQ_STACK_START +FIQ_STACK_START: + .word 0x0badc0de +#endif + +/* IRQ stack memory (calculated at run-time) + 8 bytes */ +.globl IRQ_STACK_START_IN +IRQ_STACK_START_IN: + .word 0x0badc0de + +/* + * the actual reset code + */ + +reset: + /* + * set the cpu to SVC32 mode + */ + mrs r0,cpsr + bic r0,r0,#0x1f + orr r0,r0,#0xd3 + msr cpsr,r0 + + /* + * we do sys-critical inits only at reboot, + * not when booting from ram! + */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + bl cpu_init_crit +#endif + + /* + * Relocate U-Boot to RAM + * It's copied from the old u-boot release. + */ +#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD) + adr r0, _start /* r0 <- current position of code */ + ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ + teq r0, r1 /* don't reloc during debug */ + bleq rr_exit + ldr r2, _end_ofs /* r2 <- size of u-boot */ + add r2, r0, r2 /* r2 <- source end address */ + +rr_loop: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + blo rr_loop + + /* Adjust the pc to use the correct text address */ + adr r0, _start + ldr r1, _TEXT_BASE + sub r2, pc, r0 + add r2, r2, #4 + add pc, r1, r2 + +rr_exit: +#endif /* #if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD) */ + + bl _main + +/*------------------------------------------------------------------------------*/ + +/* + * void relocate_code(addr_moni) + * + * This function relocates the monitor code. + */ + .globl relocate_code +relocate_code: + mov r6, r0 /* save addr of destination */ + + adr r0, _start + subs r9, r6, r0 /* r9 <- relocation offset */ + beq relocate_done /* skip relocation */ + mov r1, r6 /* r1 <- scratch for copy loop */ + ldr r3, _image_copy_end_ofs + add r2, r0, r3 /* r2 <- source end address */ + +copy_loop: + ldmia r0!, {r10-r11} /* copy from source address [r0] */ + stmia r1!, {r10-r11} /* copy to target address [r1] */ + cmp r0, r2 /* until source end address [r2] */ + blo copy_loop + +#ifndef CONFIG_SPL_BUILD + /* + * fix .rel.dyn relocations + */ + ldr r0, _TEXT_BASE /* r0 <- Text base */ + ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ + add r10, r10, r0 /* r10 <- sym table in FLASH */ + ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ + add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ + ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ + add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ +fixloop: + ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ + add r0, r0, r9 /* r0 <- location to fix up in RAM */ + ldr r1, [r2, #4] + and r7, r1, #0xff + cmp r7, #23 /* relative fixup? */ + beq fixrel + cmp r7, #2 /* absolute fixup? */ + beq fixabs + /* ignore unknown type of fixup */ + b fixnext +fixabs: + /* absolute fix: set location to (offset) symbol value */ + mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ + add r1, r10, r1 /* r1 <- address of symbol in table */ + ldr r1, [r1, #4] /* r1 <- symbol value */ + add r1, r1, r9 /* r1 <- relocated sym addr */ + b fixnext +fixrel: + /* relative fix: increase location by offset */ + ldr r1, [r0] + add r1, r1, r9 +fixnext: + str r1, [r0] + add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ + cmp r2, r3 + blo fixloop +#endif + +relocate_done: +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_USE_IRQ) + /* adjust exception table */ + adr r0, _undefined_instruction + adr r2, _TEXT_BASE + ldr r1, [r2] +adjustex: + ldr r3, [r0] + sub r3, r3, r1 + add r3, r6, r3 /* r6 -> relocaddr */ + str r3, [r0], #4 + cmp r0, r2 + blo adjustex + + /* relocate exception table */ + adr r0, _start + ldr r1, =CONFIG_SYS_SDRAM_BASE + adr r2, _TEXT_BASE +copyex: + ldr r3, [r0], #4 /* copy from source address [r0] */ + str r3, [r1], #4 /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + blo copyex +#endif /* #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_USE_IRQ) */ + bx lr + +#ifndef CONFIG_SPL_BUILD + +_rel_dyn_start_ofs: + .word __rel_dyn_start - _start +_rel_dyn_end_ofs: + .word __rel_dyn_end - _start +_dynsym_start_ofs: + .word __dynsym_start - _start + +#endif + + .globl c_runtime_cpu_setup +c_runtime_cpu_setup: + + bx lr + +/* + ************************************************************************* + * + * CPU_init_critical registers + * + * setup important registers + * setup memory timing + * + ************************************************************************* + */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +cpu_init_crit: + /* + * flush D cache before disabling it + */ + mov r0, #0 + mcr p15, 0, r0, c7, c14, 0 /* clean & invalidate D cache */ + mcr p15, 0, r0, c8, c7, 0 /* invalidate TLB */ + mcr p15, 0, r0, c7, c5, 0 /* invalidate I Cache */ + mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ + + /* + * disable MMU and D cache + * enable I cache if CONFIG_SYS_ICACHE_OFF is not defined + */ + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */ + bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ +#ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH + orr r0, r0, #0x00002000 /* set bit 13 (--V- ----) */ +#else + bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */ +#endif + orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ +#ifndef CONFIG_SYS_ICACHE_OFF + orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ +#endif + mcr p15, 0, r0, c1, c0, 0 + + /* + * Go setup Memory and board specific bits prior to relocation. + */ + mov ip, lr /* perserve link reg across call */ + bl lowlevel_init /* go setup pll,mux,memory */ + mov lr, ip /* restore link */ + mov pc, lr /* back to my caller */ +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ + +#ifndef CONFIG_SPL_BUILD +/* + ************************************************************************* + * + * Interrupt handling + * + ************************************************************************* + */ + +@ +@ IRQ stack frame. +@ +#define S_FRAME_SIZE 72 + +#define S_OLD_R0 68 +#define S_PSR 64 +#define S_PC 60 +#define S_LR 56 +#define S_SP 52 + +#define S_IP 48 +#define S_FP 44 +#define S_R10 40 +#define S_R9 36 +#define S_R8 32 +#define S_R7 28 +#define S_R6 24 +#define S_R5 20 +#define S_R4 16 +#define S_R3 12 +#define S_R2 8 +#define S_R1 4 +#define S_R0 0 + +#define MODE_SVC 0x13 +#define I_BIT 0x80 + +/* + * use bad_save_user_regs for abort/prefetch/undef/swi ... + * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling + */ + + .macro bad_save_user_regs + @ carve out a frame on current user stack + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 + ldr r2, IRQ_STACK_START_IN + @ get values for "aborted" pc and cpsr (into parm regs) + ldmia r2, {r2 - r3} + add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack + add r5, sp, #S_SP + mov r1, lr + stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr + mov r0, sp @ save current stack into r0 (param register) + .endm + + .macro irq_save_user_regs + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} @ Calling r0-r12 + @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. + add r8, sp, #S_PC + stmdb r8, {sp, lr}^ @ Calling SP, LR + str lr, [r8, #0] @ Save calling PC + mrs r6, spsr + str r6, [r8, #4] @ Save CPSR + str r0, [r8, #8] @ Save OLD_R0 + mov r0, sp + .endm + + .macro irq_restore_user_regs + ldmia sp, {r0 - lr}^ @ Calling r0 - lr + mov r0, r0 + ldr lr, [sp, #S_PC] @ Get PC + add sp, sp, #S_FRAME_SIZE + subs pc, lr, #4 @ return & move spsr_svc into cpsr + .endm + + .macro get_bad_stack + ldr r13, IRQ_STACK_START_IN @ setup our mode stack + + str lr, [r13] @ save caller lr in position 0 of saved stack + mrs lr, spsr @ get the spsr + str lr, [r13, #4] @ save spsr in position 1 of saved stack + mov r13, #MODE_SVC @ prepare SVC-Mode + @ msr spsr_c, r13 + msr spsr, r13 @ switch modes, make sure moves will execute + mov lr, pc @ capture return pc + movs pc, lr @ jump to next instruction & switch modes. + .endm + + .macro get_irq_stack @ setup IRQ stack + ldr sp, IRQ_STACK_START + .endm + + .macro get_fiq_stack @ setup FIQ stack + ldr sp, FIQ_STACK_START + .endm +#endif /* CONFIG_SPL_BUILD */ + +/* + * exception handlers + */ +#ifdef CONFIG_SPL_BUILD + .align 5 +do_hang: + ldr sp, _TEXT_BASE /* switch to abort stack */ +1: + bl 1b /* hang and never return */ +#else /* !CONFIG_SPL_BUILD */ + .align 5 +undefined_instruction: + get_bad_stack + bad_save_user_regs + bl do_undefined_instruction + + .align 5 +software_interrupt: + get_bad_stack + bad_save_user_regs + bl do_software_interrupt + + .align 5 +prefetch_abort: + get_bad_stack + bad_save_user_regs + bl do_prefetch_abort + + .align 5 +data_abort: + get_bad_stack + bad_save_user_regs + bl do_data_abort + + .align 5 +not_used: + get_bad_stack + bad_save_user_regs + bl do_not_used + +#ifdef CONFIG_USE_IRQ + + .align 5 +irq: + get_irq_stack + irq_save_user_regs + bl do_irq + irq_restore_user_regs + + .align 5 +fiq: + get_fiq_stack + /* someone ought to write a more effiction fiq_save_user_regs */ + irq_save_user_regs + bl do_fiq + irq_restore_user_regs + +#else + + .align 5 +irq: + get_bad_stack + bad_save_user_regs + bl do_irq + + .align 5 +fiq: + get_bad_stack + bad_save_user_regs + bl do_fiq + +#endif +#endif /* CONFIG_SPL_BUILD */ diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds index d9bbee3..ac59fec 100644 --- a/arch/arm/cpu/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -23,6 +23,8 @@ * MA 02111-1307 USA */ +#include + OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") OUTPUT_ARCH(arm) ENTRY(_start) @@ -35,6 +37,15 @@ SECTIONS { __image_copy_start = .; CPUDIR/start.o (.text*) +#ifdef CONFIG_FARADAY + /* + * Dante Su 2012.10.09: + * Reserved for the faimage v2.1. + * 1. CPUDIR/start.o: It shall never be > 4KB. + * 2. faimage header: It shall always be stored at 0x1000, and <= 1KB. + */ + . = 0x00001400; +#endif *(.text*) } diff --git a/arch/arm/include/asm/arch-a360/hardware.h b/arch/arm/include/asm/arch-a360/hardware.h new file mode 100644 index 0000000..bd2921c --- /dev/null +++ b/arch/arm/include/asm/arch-a360/hardware.h @@ -0,0 +1,72 @@ +/* + * arch/arm/include/asm/arch-a360/hardware.h + * + * (C) Copyright 2010 Faraday Technology + * Dante Su + * + * This file is released under the terms of GPL v2 and any later version. + * See the file COPYING in the root directory of the source tree for details. + */ + +#ifndef ASM_ARCH_HW_H +#define ASM_ARCH_HW_H + +#include + +#define CONFIG_SCU_BASE 0x99900000 +#define CONFIG_PMU_BASE 0x98100000 +#define CONFIG_PMU_IRQ 8 + +/* + * Timer + */ +#define CONFIG_FTTMR010_BASE 0x98400000 +#define CONFIG_FTTMR010_IRQ 19 + +/* + * UART + */ +#define CONFIG_FTUART010_BASE 0x98200000 + +/* + * Interrupt + */ +#define CONFIG_FTINTC020_BASE 0x98800000 + +/* + * WatchDog + */ +#define CONFIG_FTWDT010_BASE 0x98500000 + +/* + * NIC + */ +#define CONFIG_FTMAC110_BASE 0x90900000 + +/* + * NAND + */ +#define CONFIG_NAND_FTNANDC020_BASE 0x91000000 + +/* + * I2C + */ +#define CONFIG_FTI2C010_BASE 0x98A00000 + +/* + * SPI + */ +#define CONFIG_FTSSP010_BASE 0x98B00000 +#define CONFIG_FTSSP010_GPIO_BASE 0x98700000 + +/* + * SD/MMC + */ +#define CONFIG_FTSDC010_BASE 0x90700000 + +/* + * USB + */ +#define CONFIG_FUSBH200_BASE 0x90A00000 + +#endif diff --git a/arch/arm/include/asm/arch-a369/hardware.h b/arch/arm/include/asm/arch-a369/hardware.h new file mode 100644 index 0000000..872622c --- /dev/null +++ b/arch/arm/include/asm/arch-a369/hardware.h @@ -0,0 +1,98 @@ +/* + * arch/arm/include/asm/arch-a369/hardware.h + * + * (C) Copyright 2010 Faraday Technology + * Dante Su + * + * This file is released under the terms of GPL v2 and any later version. + * See the file COPYING in the root directory of the source tree for details. + */ + +#ifndef ASM_ARCH_HW_H +#define ASM_ARCH_HW_H + +#include + +#define CONFIG_DRAM_BASE 0x10000000 + +#define CONFIG_SRAM_BASE 0xA0000000 +#define CONFIG_SRAM_SIZE 0x00008000 + +#define CONFIG_SCU_BASE 0x92000000 +#define CONFIG_DDR_BASE 0x93100000 +#define CONFIG_AHB_BASE 0x94000000 +#define CONFIG_SMC_BASE 0x94800000 +#define CONFIG_AHBC2_BASE 0x94200000 + +/* + * Timer + */ +#define CONFIG_FTPWMTMR010_BASE 0x92300000 +#define CONFIG_FTPWMTMR010_IRQ 8 + +/* + * UART + */ +#define CONFIG_FTUART010_BASE 0x92B00000 + +/* + * Interrupt + */ +#define CONFIG_FTINTC020_BASE0 0x90100000 +#define CONFIG_FTINTC020_BASE1 0x96000000 +#define CONFIG_FTINTC020_BASE CONFIG_FTINTC020_BASE0 + +/* + * I2C + */ +#define CONFIG_FTI2C010_BASE0 0x92900000 +#define CONFIG_FTI2C010_BASE1 0x92A00000 +#define CONFIG_FTI2C010_BASE CONFIG_FTI2C010_BASE0 + +/* + * WatchDog + */ +#define CONFIG_FTWDT010_BASE 0x92200000 + +/* + * NIC + */ +#define CONFIG_FTGMAC100_BASE 0x90C00000 + +/* + * SPI + */ +#define CONFIG_FTSSP010_BASE 0x92700000 +#define CONFIG_FTSSP010_GPIO_BASE 0x92600000 /* GPIO 1 */ + +/* + * NAND + */ +#define CONFIG_NAND_FTNANDC021_BASE 0x90200000 + +/* + * LCD + */ +#define CONFIG_FTLCDC200_BASE 0x94A00000 + +/* + * SD/MMC + */ +#define CONFIG_FTSDC010_BASE1 0x90600000 +#define CONFIG_FTSDC010_BASE0 0x90500000 +#define CONFIG_FTSDC010_BASE CONFIG_FTSDC010_BASE1 + +/* + * USB + */ +#define CONFIG_FUSBH200_BASE 0x90800000 /* FUSBH200 */ +#define CONFIG_FOTG210_BASE 0x90900000 /* FOTG210 */ + + +/* + * Ext. AHB + */ +#define CONFIG_EXTAHB_BASE 0xC0000000 +#define CONFIG_FTSPI020_BASE CONFIG_EXTAHB_BASE + +#endif diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h index 440b041..a103922 100644 --- a/arch/arm/include/asm/mach-types.h +++ b/arch/arm/include/asm/mach-types.h @@ -144,6 +144,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_AKITA 744 #define MACH_TYPE_E330 753 #define MACH_TYPE_NOKIA770 755 +#define MACH_TYPE_FARADAY 758 #define MACH_TYPE_CARMEVA 769 #define MACH_TYPE_EDB9315A 772 #define MACH_TYPE_STARGATE2 774 diff --git a/board/faraday/a360evb/Makefile b/board/faraday/a360evb/Makefile new file mode 100644 index 0000000..0b0ac84 --- /dev/null +++ b/board/faraday/a360evb/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Stelian Pop +# Lead Tech Design +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := board.o clk.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/faraday/a360evb/board.c b/board/faraday/a360evb/board.c new file mode 100644 index 0000000..8d229fd --- /dev/null +++ b/board/faraday/a360evb/board.c @@ -0,0 +1,67 @@ +/* + * board/faraday/a360evb/board.c + * + * (C) Copyright 2010 Faraday Technology + * Dante Su + * + * This file is released under the terms of GPL v2 and any later version. + * See the file COPYING in the root directory of the source tree for details. + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * pinmux + */ +static void pinmux_init(void) +{ + uint32_t tmp; + + tmp = 0x00555500; + writel(cpu_to_le32(tmp), CONFIG_SCU_BASE + 0x24); + tmp = le32_to_cpu(readl(CONFIG_SCU_BASE + 0x18)) | 0x800002AA; + writel(cpu_to_le32(tmp), CONFIG_SCU_BASE + 0x18); + tmp = le32_to_cpu(readl(CONFIG_SCU_BASE + 0x1C)) | 0x82AAAAAA; + writel(cpu_to_le32(tmp), CONFIG_SCU_BASE + 0x1C); +} + +/* + * Miscellaneous platform dependent initialisations + */ + +int board_init(void) +{ + gd->bd->bi_arch_number = MACH_TYPE_FARADAY; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + pinmux_init(); + + return 0; +} + +int board_late_init(void) +{ + reset_timer(); + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = CONFIG_SYS_SDRAM_SIZE; + + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + + return 0; +} + +int board_eth_init(bd_t *bd) +{ + return ftmac110_initialize(bd); +} diff --git a/board/faraday/a360evb/clk.c b/board/faraday/a360evb/clk.c new file mode 100644 index 0000000..a3db7a4 --- /dev/null +++ b/board/faraday/a360evb/clk.c @@ -0,0 +1,52 @@ +/* + * board/faraday/a360evb/clk.c + * + * (C) Copyright 2010 Faraday Technology + * Dante Su + * + * This file is released under the terms of GPL v2 and any later version. + * See the file COPYING in the root directory of the source tree for details. + */ + +#include +#include + +static ulong clk_get_rate_ahb(void) +{ + uint32_t reg = le32_to_cpu(readl(CONFIG_PMU_BASE + 0x30)); + return CONFIG_MAIN_CLK * ((reg >> 3) & 0x3f) / 8; +} + +static ulong clk_get_rate_apb(void) +{ + return clk_get_rate_ahb() >> 1; +} + +static ulong clk_get_rate_cpu(void) +{ + uint32_t scu = le32_to_cpu(readl(CONFIG_SCU_BASE + 0x14)); + uint32_t pmu = le32_to_cpu(readl(CONFIG_PMU_BASE + 0x0C)); + ulong clk = clk_get_rate_ahb(); + ulong mul = (scu & 0x200) ? 2 : 4; + return (pmu & 0x02) ? (clk * mul) : clk; +} + +ulong clk_get_rate(char *id) +{ + ulong clk = 0; + + if (!strcmp(id, "AHB")) + clk = clk_get_rate_ahb(); + else if (!strcmp(id, "APB")) + clk = clk_get_rate_apb(); + else if (!strcmp(id, "CPU")) + clk = clk_get_rate_cpu(); + else if (!strcmp(id, "SDC")) + clk = clk_get_rate_ahb(); + else if (!strcmp(id, "I2C")) + clk = clk_get_rate_apb(); + else if (!strcmp(id, "SPI") || !strcmp(id, "SSP")) + clk = clk_get_rate_apb(); + + return clk; +} diff --git a/board/faraday/a360evb/config.mk b/board/faraday/a360evb/config.mk new file mode 100644 index 0000000..eb1a258 --- /dev/null +++ b/board/faraday/a360evb/config.mk @@ -0,0 +1,33 @@ +# +# (C) Copyright 2010 +# Dante Su +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +######################################################################### + +ALL += $(obj)u-boot.img + +# Environment variables in NAND +#ifeq ($(ENV),NAND) +#PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND +#else +#PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH +#endif diff --git a/board/faraday/a360evb/lowlevel_init.S b/board/faraday/a360evb/lowlevel_init.S new file mode 100644 index 0000000..1ead608 --- /dev/null +++ b/board/faraday/a360evb/lowlevel_init.S @@ -0,0 +1,33 @@ +/* + * Board specific setup info + * + * (C) Copyright 2010 + * Faraday Technology Inc. + * Dante Su + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* Set up the platform, once the cpu has been initialized */ +.globl lowlevel_init +lowlevel_init: + mov pc,lr diff --git a/board/faraday/a369evb/Makefile b/board/faraday/a369evb/Makefile new file mode 100644 index 0000000..0b0ac84 --- /dev/null +++ b/board/faraday/a369evb/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Stelian Pop +# Lead Tech Design +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := board.o clk.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/faraday/a369evb/board.c b/board/faraday/a369evb/board.c new file mode 100644 index 0000000..b818071 --- /dev/null +++ b/board/faraday/a369evb/board.c @@ -0,0 +1,178 @@ +/* + * board/faraday/a369evb/board.c + * + * (C) Copyright 2010 Faraday Technology + * Dante Su + * + * This file is released under the terms of GPL v2 and any later version. + * See the file COPYING in the root directory of the source tree for details. + */ + +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define SOC_READ(r) le32_to_cpu(readl(r)) +#define SOC_WRITE(v, r) writel(cpu_to_le32(v), r) +#define SOC_SETBITS(m, r) setbits_le32(r, m) +#define SOC_CLRBITS(m, r) clrbits_le32(r, m) + +/* + * System Control Uint (pinmux) + */ +static void scu_init(void) +{ + /* If it's external CPU mode */ + if (SOC_READ(CONFIG_SCU_BASE + 0x204) & BIT_MASK(2)) { + SOC_WRITE(0xc0008000, CONFIG_SCU_BASE + 0x028); + SOC_SETBITS(BIT_MASK(14), CONFIG_SCU_BASE + 0x200); + } else { +#if CONFIG_SUPP_EXTAHB + /* Enable external AHB */ + SOC_WRITE(0x40000000, CONFIG_SCU_BASE + 0x028); + SOC_WRITE(0x00001078, CONFIG_SCU_BASE + 0x200); + SOC_CLRBITS(0xf0, CONFIG_SCU_BASE + 0x228); + SOC_SETBITS(0x80, CONFIG_SCU_BASE + 0x228); +#else + /* Enable SD1 */ + SOC_WRITE(0x00000241, CONFIG_SCU_BASE + 0x238); +#endif + } + + /* Clock Setup: SD = 133MHz, SSP = APB (SPI mode) */ + SOC_WRITE(0x000A0A0A, CONFIG_SCU_BASE + 0x22C); + + /* Enable LCD for I2C/TVEncode work-around */ + /* ... Clock div = (31+1) */ + SOC_WRITE(0x1f00, CONFIG_FTLCDC200_BASE + 0x10c); + /* ... Enable LCD */ + SOC_WRITE(0x0003, CONFIG_FTLCDC200_BASE + 0x000); +} + +/* + * Static Memory Controller (NOR Flash) + */ +static void smc_init(void) +{ + /* 1. NOR Flash Setup */ + /* Bank 0: base=0x00000000, size=64MB, 16bits */ + SOC_WRITE(BIT_MASK(28) | (6 << 4) | 1, CONFIG_SMC_BASE + 0x00); + /* Bank 0: worst timing */ + SOC_WRITE(0x0f1ff3ff, CONFIG_SMC_BASE + 0x04); + + /* 2. Unused Area */ + SOC_WRITE(0x00000000, CONFIG_SMC_BASE + 0x08); + SOC_WRITE(0x0f1ff3ff, CONFIG_SMC_BASE + 0x0C); + SOC_WRITE(0x00000000, CONFIG_SMC_BASE + 0x10); + SOC_WRITE(0x0f1ff3ff, CONFIG_SMC_BASE + 0x14); + SOC_WRITE(0x00000000, CONFIG_SMC_BASE + 0x18); + SOC_WRITE(0x0f1ff3ff, CONFIG_SMC_BASE + 0x1C); +} + +/* + * Miscellaneous platform dependent initialisations + */ + +int board_init(void) +{ + gd->bd->bi_arch_number = MACH_TYPE_FARADAY; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + scu_init(); + smc_init(); + return 0; +} + +int board_late_init(void) +{ + reset_timer(); + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = CONFIG_SYS_SDRAM_SIZE; + + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + + return 0; +} + +int board_eth_init(bd_t *bd) +{ +#ifdef CONFIG_USB_ETHER + return usb_eth_initialize(bd); +#elif defined(CONFIG_FTGMAC100) + return ftgmac100_initialize(bd); +#endif +} + +int board_mmc_init(bd_t *bis) +{ +#if defined(CONFIG_FTSDC010) || defined(CONFIG_FTSDC010_MCI) + return ftsdc010_mmc_init(0); +#else + return 0; +#endif +} + +int board_nand_init(struct nand_chip *chip) +{ + int ret = 0; +#ifdef CONFIG_NAND_FTNANDC021 + uint32_t reg = SOC_READ(CONFIG_SCU_BASE + 0x204); + + /* page shift */ + switch ((reg & 0x180) >> 7) { + case 0: + chip->page_shift = 9; /* 512 */ + break; + case 1: + chip->page_shift = 11; /* 2048 */ + break; + case 2: + case 3: + chip->page_shift = 12; /* 4096 */ + break; + } + + /* block shift */ + switch ((reg & 0x600) >> 9) { + case 0: /* 16 pages */ + chip->phys_erase_shift = chip->page_shift + 4; + break; + case 1: /* 32 pages */ + chip->phys_erase_shift = chip->page_shift + 5; + break; + case 2: /* 64 pages */ + chip->phys_erase_shift = chip->page_shift + 6; + break; + case 3: /* 128 pages */ + chip->phys_erase_shift = chip->page_shift + 7; + break; + } + + /* address cycle */ + switch ((reg & 0x60) >> 5) { + case 0: /* NANDC_AP_3C: */ + chip->priv = (void *)3; + break; + case 1: /* NANDC_AP_4C: */ + chip->priv = (void *)4; + break; + case 2: /* NANDC_AP_5C: */ + case 3: + chip->priv = (void *)5; + break; + } + + ret = ftnandc021_probe(chip); +#endif + return ret; +} diff --git a/board/faraday/a369evb/clk.c b/board/faraday/a369evb/clk.c new file mode 100644 index 0000000..1fb73f7 --- /dev/null +++ b/board/faraday/a369evb/clk.c @@ -0,0 +1,81 @@ +/* + * board/faraday/a369evb/clk.c + * + * (C) Copyright 2010 Faraday Technology + * Dante Su + * + * This file is released under the terms of GPL v2 and any later version. + * See the file COPYING in the root directory of the source tree for details. + */ + +#include +#include + +static ulong clk_get_rate_ahb(void) +{ + uint32_t reg = 0, mul = 4; + ulong ts; + + /* Wait until PLL1 becomes stable or 5 ms timeout */ + ts = get_timer(0); + do { + reg = le32_to_cpu(readl(CONFIG_SCU_BASE + 0x20)); + } while (!(reg & BIT_MASK(1)) && (get_timer(ts) < 5)); + + mul = (reg >> 24) & 0x3f; + + return (CONFIG_MAIN_CLK * mul) >> 3; +} + +static ulong clk_get_rate_apb(void) +{ + return clk_get_rate_ahb() >> 1; +} + +static ulong clk_get_rate_cpu(void) +{ + ulong clk = clk_get_rate_ahb(); + +#ifndef CONFIG_A369_FA606TE_PLATFORM + uint32_t reg; + + /* If it's an internal CPU */ + reg = le32_to_cpu(readl(CONFIG_SCU_BASE + 0x204)); + if (!(reg & BIT_MASK(2))) { + reg = le32_to_cpu(readl(CONFIG_SCU_BASE + 0x08)); + switch ((reg >> 3) & 3) { + case 0: + clk = clk << 0; + break; + case 1: + clk = clk << 1; + break; + default: + clk = clk << 2; + break; + } + } +#endif + + return clk; +} + +ulong clk_get_rate(char *id) +{ + ulong clk = 0; + + if (!strcmp(id, "AHB")) + clk = clk_get_rate_ahb(); + else if (!strcmp(id, "APB")) + clk = clk_get_rate_apb(); + else if (!strcmp(id, "CPU")) + clk = clk_get_rate_cpu(); + else if (!strcmp(id, "SDC")) + clk = clk_get_rate_ahb(); + else if (!strcmp(id, "I2C")) + clk = clk_get_rate_apb(); + else if (!strcmp(id, "SPI") || !strcmp(id, "SSP")) + clk = clk_get_rate_apb(); + + return clk; +} diff --git a/board/faraday/a369evb/config.mk b/board/faraday/a369evb/config.mk new file mode 100644 index 0000000..eb1a258 --- /dev/null +++ b/board/faraday/a369evb/config.mk @@ -0,0 +1,33 @@ +# +# (C) Copyright 2010 +# Dante Su +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +######################################################################### + +ALL += $(obj)u-boot.img + +# Environment variables in NAND +#ifeq ($(ENV),NAND) +#PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND +#else +#PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH +#endif diff --git a/board/faraday/a369evb/lowlevel_init.S b/board/faraday/a369evb/lowlevel_init.S new file mode 100644 index 0000000..a55fddb --- /dev/null +++ b/board/faraday/a369evb/lowlevel_init.S @@ -0,0 +1,136 @@ +/* + * Board specific setup info + * + * (C) Copyright 2010 + * Faraday Technology Inc. + * Dante Su + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + + .macro _v3_mw32 + + ldr r0, =0x1008 + ldr r3, =0x1108 +_v3_mw32_loop: + cmp r0, r3 + movhs r1, #0 + ldrlo r1, [r0, #0] + ldrlo r2, [r0, #4] + teq r1, #0 + strne r2, [r1, #0] + addne r0, #8 + bne _v3_mw32_loop + + .endm /* _v3_mw32 */ + + .macro _sdram_enable + + /* Clear SDRAM CKE, GPIO Hold, READ Hold */ + ldr r0, =CONFIG_SCU_BASE + mov r1, #7 + str r1, [r0, #0x14] + + /* Wait until sdram ready */ + ldr r0, =CONFIG_DDR_BASE +_sdram_wait: + ldr r1, [r0, #0x04] + teq r1, #0x100 + bne _sdram_wait + + .endm /* _sdram_enable */ + +/* Set up the platform, once the cpu has been initialized */ +.globl lowlevel_init +lowlevel_init: + /* Check image header */ + ldr r1, =0x1000 + ldr r0, [r1, #0] + ldr r1, =0x00484946 /* "FIH\0" */ + ldr r2, =0x33333639 /* "3369" */ + teq r0, r1 + teqne r0, r2 + bne _exit + _v3_mw32 + _sdram_enable + +#if 1 + /* Create a shadow copy onto SDRAM (limited to 512K) */ + mov r0, #0 /* r0 <- start of source */ + ldr r1, =CONFIG_AHB_BASE + ldr r2, [r1,#0x18] + bic r1, r2, #0x000f0000 /* r1 <- SDRAM base */ + mov r2, #0x80000 /* r2 <- source end address (512KB) */ + +_copy_loop: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + ble _copy_loop +#else + /* Adjust lr(r14) to the remapped address */ + ldr r0, =CONFIG_AHB_BASE + ldr r1, [r0,#0x18] /* r1 = AHB slave 6 */ + bic r1, r1, #0xff000000 + bic r1, r1, #0x00f00000 + lsr r1, r1, #16 + add r1, r1, #20 + mov r2, #1 + lsl r2, r2, r1 + add lr, lr, r2 +#endif + + /* AHB remap */ + mov r0, #0 + ldr r1, =CONFIG_AHB_BASE + ldr r2, =CONFIG_DDR_BASE + /* magic (r5) = REG32(0x00) XOR 0xFFFFFFFF */ + ldr r5, [r0, #0] + ldr r3, =0xffffffff + eor r5, r5, r3 + /* r3 = REG32(CONFIG_IOBASE_DDR + 0x10) & 0x00FFFFFF */ + ldr r3, [r2, #0x10] + bic r3, #0xff000000 + /* r4 = 0x00100f01 */ + ldr r4, =0x00100f01 + + /* + * invalidate i-cache all to make sure the codes bellow + * to be fetched into a single 32-bytes cache line + */ + mcr p15, 0, r0, c7, c5, 0 + + .align 5 + + str r3, [r2, #0x10] /* REG32(CONFIG_IOBASE_DDR + 0x10) &= 0x00FFFFFF */ + str r4, [r1, #0x88] /* REG32(CONFIG_IOBASE_AHB + 0x88) = 0x00100F01 */ + +_remap_wait: + str r5, [r0, #0] + ldr r1, [r0, #0] + teq r1, r5 + bne _remap_wait /* while(magic != REG32(addr)) */ + +_exit: + mov pc, lr diff --git a/boards.cfg b/boards.cfg index f785da8..e2de722 100644 --- a/boards.cfg +++ b/boards.cfg @@ -73,6 +73,9 @@ mini2440 arm arm920t mini2440 friendl VCMA9 arm arm920t vcma9 mpl s3c24x0 smdk2410 arm arm920t - samsung s3c24x0 omap1510inn arm arm925t - ti +a360 arm faraday a360evb faraday a360 +a369 arm faraday a369evb faraday a369 +a369_fa606te arm faraday a369evb faraday a369 integratorap_cm926ejs arm arm926ejs integrator armltd - integratorap:CM926EJ_S integratorcp_cm926ejs arm arm926ejs integrator armltd - integratorcp:CM924EJ_S aspenite arm arm926ejs - Marvell armada100 diff --git a/include/common.h b/include/common.h index 0cfa6a8..fa134f3 100644 --- a/include/common.h +++ b/include/common.h @@ -112,6 +112,9 @@ typedef volatile unsigned char vu_char; #ifdef CONFIG_SOC_DA8XX #include #endif +#ifdef CONFIG_FARADAY +#include +#endif #include #include @@ -257,6 +260,16 @@ typedef void (interrupt_handler_t)(void *); const typeof( ((type *)0)->member ) *__mptr = (ptr); \ (type *)( (char *)__mptr - offsetof(type,member) );}) +#ifdef CONFIG_FARADAY +/* board/faraday/xxx/clk.c */ +extern ulong clk_get_rate(char *id); + +/* arch/arm/cpu/faraday/xxx/interrupt.c */ +extern void irq_set_trigger(int irq, int edge, int low); +extern void irq_enable(int irq); +extern void irq_disable(int irq); +#endif + /* * Function Prototypes */ diff --git a/include/configs/a360.h b/include/configs/a360.h new file mode 100644 index 0000000..19a116e --- /dev/null +++ b/include/configs/a360.h @@ -0,0 +1,185 @@ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * Hardware Resources (i.e. iobase, irq) + */ +#include + +#define CONFIG_A360_PLATFORM 1 +#define CONFIG_SYS_NO_FLASH 1 +/* #define CONFIG_USE_IRQ 1 */ + +/* + * Warning: changing CONFIG_SYS_TEXT_BASE requires + * adapting the initial boot program. + * Since the linker has to swallow that define, we must use a pure + * hex number here! + */ +#define CONFIG_SYS_TEXT_BASE 0x00800000 +/* #define CONFIG_BOARD_EARLY_INIT_F 1 */ +#define CONFIG_BOARD_LATE_INIT 1 + +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_SIZE SZ_256M + +#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + SZ_16M) +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + SZ_32M) + +/* + * Initial stack pointer: GENERATED_GBL_DATA_SIZE in internal SRAM. + * Inside the board_init_f, the gd is first assigned to + * (CONFIG_SYS_INIT_SP_ADDR) & ~0x07) and then relocated to DRAM + * while calling relocate_code. + */ +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + SZ_4K - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_MALLOC_LEN SZ_4M + +#define CONFIG_STACKSIZE SZ_512K +#define CONFIG_STACKSIZE_IRQ SZ_32K +#define CONFIG_STACKSIZE_FIQ SZ_32K + +/* + * CPU + */ +#define CONFIG_ARCH_CPU_INIT 1 +#define CONFIG_DISPLAY_CPUINFO 1 +#define CONFIG_FARADAY 1 +#define CONFIG_SYS_CACHELINE_SIZE 32 + +/* + * Interrupt + */ +#if CONFIG_USE_IRQ +#define CONFIG_FTINTC020 1 +#define CONFIG_PIC_BASE CONFIG_FTINTC020_BASE +#endif + +/* + * Timer + */ +#define CONFIG_FTTMR010 1 +#define CONFIG_TIMER_BASE CONFIG_FTTMR010_BASE +#define CONFIG_TIMER_IRQ CONFIG_FTTMR010_IRQ + +/* + * WatchDog + */ +#define CONFIG_FTWDT010 1 + +/* + * Clock + */ +#define CONFIG_MAIN_CLK 40000000 +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_MONITOR_LEN SZ_256K + +/* + * U-Boot general commands + */ +#define CONFIG_CMD_AUTOSCRIPT 1 /* Autoscript Support */ +#define CONFIG_CMD_BDI 1 /* bdinfo */ +#define CONFIG_CMD_BOOTD 1 /* bootd */ +#define CONFIG_CMD_ECHO 1 /* echo arguments */ +#define CONFIG_CMD_ENV 1 /* saveenv */ +#define CONFIG_CMD_IMI 1 /* iminfo */ +#define CONFIG_CMD_MEMORY 1 /* md mm nm mw ... */ +#define CONFIG_CMD_NET 1 /* bootp, tftpboot, rarpboot */ +#define CONFIG_CMD_RUN 1 /* run command in env variable */ +#define CONFIG_CMD_CACHE 1 /* cache enable/disable command */ +#define CONFIG_CMD_ELF 1 + +/* + * Linux kernel command line options + */ +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Serial Info + */ +#define CONFIG_SYS_NS16550 1 +#define CONFIG_SYS_NS16550_SERIAL 1 +#define CONFIG_SYS_NS16550_CLK 18432000 +#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_BASE +#define CONFIG_SYS_NS16550_MEM32 1 +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 38400 +#undef CONFIG_HWFLOW +#undef CONFIG_MODEM_SUPPORT + +/* + * NIC driver + */ +#define CONFIG_FTMAC110 1 +#define CONFIG_ETHADDR 00:84:14:72:61:69 /* used by env_common.c */ +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 10.0.0.123 +#define CONFIG_SERVERIP 10.0.0.128 +#define CONFIG_MII 1 +#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_DRIVER_ETHER 1 +#define CONFIG_CMD_MII 1 +#define CONFIG_CMD_PING 1 + +/* + * Shell + */ +#define CONFIG_SYS_HUSH_PARSER 1 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT "=> " +#define CONFIG_AUTO_COMPLETE 1 +#define CONFIG_CMDLINE_EDITING 1 + +/* + * Environment + */ +#define CONFIG_ENV_IS_NOWHERE 1 +#define CONFIG_ENV_OFFSET 0x07FC0000 +#define CONFIG_ENV_OFFSET_REDUND 0x07FE0000 +#define CONFIG_ENV_SIZE 0x00020000 + +/* + * System + */ +#define CONFIG_SYS_LOAD_ADDR 0x01000000 /* default load address */ +#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 } +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* max number of command args */ +#define CONFIG_SYS_MAXARGS 32 +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_LZMA 1 +#define CONFIG_TIMESTAMP 1 +#define CONFIG_SYS_LONGHELP 1 +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +/* + * FAT (USB & MMC) + */ +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_CMD_FAT 1 +#define CONFIG_PARTITIONS 1 + +/* + * USB + */ +#define CONFIG_USB_EHCI_FUSBH200 1 +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1 +#define CONFIG_USB_EHCI 1 +#define CONFIG_USB_EHCI_FARADAY 1 +#define CONFIG_EHCI_IS_TDI 1 +#if !defined(CONFIG_SYS_DCACHE_OFF) +#define CONFIG_EHCI_DCACHE 1 +#endif +#define CONFIG_CMD_USB 1 +#define CONFIG_USB_STORAGE 1 + +#endif diff --git a/include/configs/a369.h b/include/configs/a369.h new file mode 100644 index 0000000..b884b9c --- /dev/null +++ b/include/configs/a369.h @@ -0,0 +1,41 @@ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_A369_PLATFORM 1 + +/* Support external AHB */ +/* +#define CONFIG_SUPP_EXTAHB 1 +*/ + +/* Support USB RNDIS Ethernet */ +/* +#define CONFIG_SUPP_USB_RNDIS 1 +*/ + +/* Disable NOR flash support */ +#define CONFIG_SYS_NO_FLASH 1 + +/* Support interrupt */ +/* +#define CONFIG_USE_IRQ 1 +*/ + +/* Disable MMU/D-CACHE */ +/* +#define CONFIG_SYS_DCACHE_OFF 1 +*/ + +#ifndef CONFIG_SYS_DCACHE_OFF +#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH 1 +#endif + +/* Transfer the control to the built-in slave cpu: FA606TE */ +#define CONFIG_CMD_FA606 1 + +/* Hardware Resources (i.e. iobase, irq) */ +#include + +#include "a369_defaults.h" + +#endif diff --git a/include/configs/a369_defaults.h b/include/configs/a369_defaults.h new file mode 100644 index 0000000..24219da --- /dev/null +++ b/include/configs/a369_defaults.h @@ -0,0 +1,295 @@ +#ifndef __CONFIG_A369_DEFAULTS_H +#define __CONFIG_A369_DEFAULTS_H + +/* + * Autoboot + */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTCOMMAND "bootfa nand linux" + +/* + * Warning: changing CONFIG_SYS_TEXT_BASE requires + * adapting the initial boot program. + * Since the linker has to swallow that define, we must use a pure + * hex number here! + */ +#define CONFIG_SYS_TEXT_BASE 0x00800000 +/* #define CONFIG_BOARD_EARLY_INIT_F 1 */ +#define CONFIG_BOARD_LATE_INIT 1 + +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_SIZE SZ_512M + +#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + SZ_16M) +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + SZ_32M) + +/* + * Initial stack pointer: GENERATED_GBL_DATA_SIZE in internal SRAM. + * Inside the board_init_f, the gd is first assigned to + * (CONFIG_SYS_INIT_SP_ADDR) & ~0x07) and then relocated to DRAM + * while calling relocate_code. + */ +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + SZ_4K - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_MALLOC_LEN SZ_8M + +#define CONFIG_STACKSIZE SZ_512K +#define CONFIG_STACKSIZE_IRQ SZ_32K +#define CONFIG_STACKSIZE_FIQ SZ_32K + +/* + * CPU + */ +#define CONFIG_ARCH_CPU_INIT 1 +#define CONFIG_DISPLAY_CPUINFO 1 +#define CONFIG_FARADAY 1 +#define CONFIG_SYS_CACHELINE_SIZE 32 + +/* + * Interrupt + */ +#if CONFIG_USE_IRQ +# define CONFIG_FTINTC020 1 +# ifdef CONFIG_A369_PLATFORM +# define CONFIG_PIC_BASE CONFIG_FTINTC020_BASE +# else +# define CONFIG_PIC_BASE CONFIG_FTINTC020_BASE1 +# endif +#endif + +/* + * Timer + */ +#define CONFIG_FTPWMTMR010 1 +#define CONFIG_TIMER_BASE CONFIG_FTPWMTMR010_BASE +#define CONFIG_TIMER_IRQ CONFIG_FTPWMTMR010_IRQ + +/* + * Clock + */ +#define CONFIG_MAIN_CLK 33000000 +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_MONITOR_LEN SZ_256K + +/* + * U-Boot general commands + */ +#define CONFIG_CMD_AUTOSCRIPT 1 /* Autoscript Support */ +#define CONFIG_CMD_BDI 1 /* bdinfo */ +#define CONFIG_CMD_BOOTD 1 /* bootd */ +#define CONFIG_CMD_ECHO 1 /* echo arguments */ +#define CONFIG_CMD_ENV 1 /* saveenv */ +#define CONFIG_CMD_IMI 1 /* iminfo */ +#define CONFIG_CMD_MEMORY 1 /* md mm nm mw ... */ +#define CONFIG_CMD_NET 1 /* bootp, tftpboot, rarpboot */ +#define CONFIG_CMD_RUN 1 /* run command in env variable */ +#define CONFIG_CMD_CACHE 1 /* cache enable/disable command */ +#define CONFIG_CMD_ELF 1 + +/* + * Linux kernel command line options + */ +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Serial Info + */ +#define CONFIG_SYS_NS16550 1 +#define CONFIG_SYS_NS16550_SERIAL 1 +#define CONFIG_SYS_NS16550_CLK 18432000 +#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_BASE +#define CONFIG_SYS_NS16550_MEM32 1 +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 38400 +#undef CONFIG_HWFLOW +#undef CONFIG_MODEM_SUPPORT + +/* + * NIC driver + */ +#define CONFIG_FTGMAC100 1 +#define CONFIG_PHY_MAX_ADDR 32 /* used by Ratbert's ftgmac100 only */ +#define CONFIG_FTGMAC100_EGIGA 1 /* used by Ratbert's ftgmac100 only */ +#define CONFIG_ETHADDR 00:84:14:72:61:69 /* used by env_common.c */ +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 10.0.0.123 +#define CONFIG_SERVERIP 10.0.0.128 +#define CONFIG_MII 1 +#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_DRIVER_ETHER 1 +#define CONFIG_CMD_MII 1 +#define CONFIG_CMD_PING 1 + +/* + * I2C Controller + */ +#define CONFIG_FTI2C010 1 +#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C_SPEED 5000 +#define CONFIG_SYS_I2C_SLAVE 0 +#define CONFIG_CMD_I2C 1 +#define CONFIG_I2C_CMD_TREE 1 +#define CONFIG_I2C_MULTI_BUS 1 +#define CONFIG_SYS_MAX_I2C_BUS 2 + +/* + * EEPROM + */ +#define CONFIG_CMD_EEPROM 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 +#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_ENV_EEPROM_IS_ON_I2C 1 + +/* + * SPI + */ +#define CONFIG_FTSSP010_SPI 1 +#define CONFIG_FTSSP010_GPIO_PIN 27 +#define CONFIG_SPI 1 +#define CONFIG_HARD_SPI 1 +#define CONFIG_CMD_SPI 1 +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 25000000 +#define CONFIG_DEFAULT_SPI_MODE 0 + +/* + * SPI Flash + */ +#define CONFIG_FTSSP010_SPI 1 +/* +#define CONFIG_FTSPI020 1 +*/ +#ifndef CONFIG_FTSPI020 +#define CONFIG_SPI_FLASH 1 +#define CONFIG_SPI_FLASH_MACRONIX 1 +#define CONFIG_SPI_FLASH_WINBOND 1 +#endif /* #ifndef CONFIG_FTSPI020 */ +#define CONFIG_CMD_SF 1 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SF_DEFAULT_SPEED 25000000 + +/* + * NOR Flash + */ +#ifndef CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_FLASH_BASE 0x20000000 +#define PHYS_FLASH_SIZE SZ_64M +#define CONFIG_SYS_FLASH_CFI 1 +#define CONFIG_FLASH_CFI_DRIVER 1 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* max. sector number */ +#define CFG_FLASH_EMPTY_INFO 1 /* print 'E' for empty sector on flinfo */ +#define CONFIG_CMD_IMLS 1 +#define CONFIG_CMD_FLASH 1 +#endif /* !CONFIG_SYS_NO_FLASH */ + +/* + * NAND Flash + */ +#define CONFIG_NAND_FTNANDC021 1 +#define CONFIG_FTNANDC021_ACTIMING_1 0x02240264 +#define CONFIG_FTNANDC021_ACTIMING_2 0x42054209 +#define CONFIG_CMD_NAND 1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define CONFIG_SYS_NAND_BASE CONFIG_NAND_FTNANDC021_BASE +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_NAND_FTNANDC021_BASE } +#define CONFIG_MTD_NAND_VERIFY_WRITE 1 + +/* + * Shell + */ +#define CONFIG_SYS_HUSH_PARSER 1 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT "=> " +#define CONFIG_AUTO_COMPLETE 1 +#define CONFIG_CMDLINE_EDITING 1 + +/* + * Environment + */ +#define CONFIG_CMD_SAVEENV 1 +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_OFFSET 0x07FC0000 +#define CONFIG_ENV_OFFSET_REDUND 0x07FE0000 +#define CONFIG_ENV_SIZE 0x00020000 + +/* + * System + */ +#define CONFIG_SYS_LOAD_ADDR 0x01000000 /* default load address */ +#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 } +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Max number of command args */ +#define CONFIG_SYS_MAXARGS 32 +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_LZMA 1 +#define CONFIG_TIMESTAMP 1 +#define CONFIG_SYS_LONGHELP 1 +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +/* + * FAT (USB & MMC) + */ +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_CMD_FAT 1 +#define CONFIG_PARTITIONS 1 + +/* + * MMC (FTSDC010) + */ +#if 1 +#define CONFIG_FTSDC010_MCI 1 +#define CONFIG_FTSDC010_SDIO 1 /* The hardware core supports SDIO */ +#else +#define CONFIG_FTSDC010 1 +#define CONFIG_FTSDC010_SDIO 1 /* The hardware core supports SDIO */ +#define CONFIG_FTSDC010_NUMBER 1 +#define CONFIG_SYS_CLK_FREQ 133000000 /* AHB clock */ +#endif +#define CONFIG_MMC 1 +#define CONFIG_CMD_MMC 1 +#define CONFIG_GENERIC_MMC 1 + +/* + * USB EHCI Host + */ +#define CONFIG_USB_EHCI_BASE CONFIG_FUSBH200_BASE +#if CONFIG_SUPP_USB_RNDIS +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#else +#define CONFIG_USB_EHCI_BASE1 CONFIG_FOTG210_BASE +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1 +#define CONFIG_USB_EHCI 1 +#define CONFIG_USB_EHCI_FARADAY 1 +#define CONFIG_EHCI_IS_TDI 1 +#define CONFIG_CMD_USB 1 +#define CONFIG_USB_STORAGE 1 + +/* + * USB Gadget + */ +#if CONFIG_SUPP_USB_RNDIS +#define CONFIG_USB_GADGET 1 +#define CONFIG_USB_GADGET_FOTG210 1 +#define CONFIG_USB_GADGET_DUALSPEED 1 +#define CONFIG_USB_ETHER 1 +#define CONFIG_USB_ETH_RNDIS 1 +#define CONFIG_USBNET_DEV_ADDR "00:41:71:00:00:55" /* U-Boot */ +#define CONFIG_USBNET_HOST_ADDR "00:41:71:00:00:54" /* Host PC */ +#endif + +#endif diff --git a/include/configs/a369_fa606te.h b/include/configs/a369_fa606te.h new file mode 100644 index 0000000..8c90fd8 --- /dev/null +++ b/include/configs/a369_fa606te.h @@ -0,0 +1,32 @@ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_A369_FA606TE_PLATFORM 1 + +/* Support external AHB */ +/* +#define CONFIG_SUPP_EXTAHB 1 +*/ + +/* Support USB RNDIS Ethernet */ +/* +#define CONFIG_SUPP_USB_RNDIS 1 +*/ + +/* Disable NOR flash support */ +#define CONFIG_SYS_NO_FLASH 1 + +/* Support interrupt */ +/* +#define CONFIG_USE_IRQ 1 +*/ + +/* Disable CPU MMU support */ +#define CONFIG_SYS_DCACHE_OFF 1 /* Disable MMU/D-CACHE */ + +/* Hardware Resources (i.e. iobase, irq) */ +#include + +#include "a369_defaults.h" + +#endif diff --git a/include/faraday/fttmr010.h b/include/faraday/fttmr010.h index 72abcb3..ef10f31 100644 --- a/include/faraday/fttmr010.h +++ b/include/faraday/fttmr010.h @@ -57,6 +57,16 @@ struct fttmr010 { #define FTTMR010_TM1_CLOCK (1 << 1) #define FTTMR010_TM1_ENABLE (1 << 0) +#define FTTMR010_TM1_CRMASK \ + (FTTMR010_TM1_UPDOWN | FTTMR010_TM1_OFENABLE \ + | FTTMR010_TM1_CLOCK | FTTMR010_TM1_ENABLE) +#define FTTMR010_TM2_CRMASK \ + (FTTMR010_TM2_UPDOWN | FTTMR010_TM2_OFENABLE \ + | FTTMR010_TM2_CLOCK | FTTMR010_TM2_ENABLE) +#define FTTMR010_TM3_CRMASK \ + (FTTMR010_TM3_UPDOWN | FTTMR010_TM3_OFENABLE \ + | FTTMR010_TM3_CLOCK | FTTMR010_TM3_ENABLE) + /* * Timer Interrupt State & Mask Registers */ @@ -70,4 +80,11 @@ struct fttmr010 { #define FTTMR010_TM1_MATCH2 (1 << 1) #define FTTMR010_TM1_MATCH1 (1 << 0) +#define FTTMR010_TM1_ISRMASK \ + (FTTMR010_TM1_OVERFLOW | FTTMR010_TM1_MATCH2 | FTTMR010_TM1_MATCH1) +#define FTTMR010_TM2_ISRMASK \ + (FTTMR010_TM2_OVERFLOW | FTTMR010_TM2_MATCH2 | FTTMR010_TM2_MATCH1) +#define FTTMR010_TM3_ISRMASK \ + (FTTMR010_TM3_OVERFLOW | FTTMR010_TM3_MATCH2 | FTTMR010_TM3_MATCH1) + #endif /* __FTTMR010_H */