From patchwork Thu Apr 18 09:21:41 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Bruel X-Patchwork-Id: 237568 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "localhost", Issuer "www.qmailtoaster.com" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 04D9A2C0085 for ; Thu, 18 Apr 2013 19:21:58 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; q=dns; s=default; b=a2mmnZ/2HVXwXvARAPx5fGKfrooTPG8QAMA3w8UBlY3 KWdWp+AoqOUZkK1/ll17WtIjpungIAj4AIOjzNqfRawTGzZfMgawe5Mr0Pts/Hl4 YTt2yHl2aLmnbX+bAXE9e9wW695ZV2vR9ACpTTD+DL0QGHg6yGQW1gtQkq5sBJBM = DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; s=default; bh=csHHWlCF4OVKAJvEAvNgCb9vLII=; b=PDDvdxG1IDXIXy20a 6dkpYWyN0PWjFmojR8vcOaH2H4RRWPIV0BH3hd3MO9zCDUb4SxaXpo5INz1f73OO fwTMXCb4Btskj+neg3dh6Wo+20xyc5zUeRZUlRqgLfM81pBwTGSUoADHT3Y3Sqwv DkR2FYjFacm46DlecsrerLa1uY= Received: (qmail 17041 invoked by alias); 18 Apr 2013 09:21:51 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 17031 invoked by uid 89); 18 Apr 2013 09:21:51 -0000 X-Spam-SWARE-Status: No, score=-3.4 required=5.0 tests=AWL, BAYES_00, KHOP_RCVD_UNTRUST, RCVD_IN_HOSTKARMA_W, RCVD_IN_HOSTKARMA_WL autolearn=ham version=3.3.1 Received: from eu1sys200aog118.obsmtp.com (HELO eu1sys200aog118.obsmtp.com) (207.126.144.145) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Thu, 18 Apr 2013 09:21:50 +0000 Received: from beta.dmz-eu.st.com ([164.129.1.35]) (using TLSv1) by eu1sys200aob118.postini.com ([207.126.147.11]) with SMTP ID DSNKUW+7KJXYpuHY+hFJcgl5LVCgUhH9rpGJ@postini.com; Thu, 18 Apr 2013 09:21:49 UTC Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id C1B551A3; Thu, 18 Apr 2013 09:21:43 +0000 (GMT) Received: from Webmail-eu.st.com (safex1hubcas5.st.com [10.75.90.71]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 40E364D51; Thu, 18 Apr 2013 09:21:39 +0000 (GMT) Received: from [164.129.122.89] (164.129.122.89) by webmail-eu.st.com (10.75.90.13) with Microsoft SMTP Server (TLS) id 8.3.279.5; Thu, 18 Apr 2013 11:21:42 +0200 Message-ID: <516FBB25.8080103@st.com> Date: Thu, 18 Apr 2013 11:21:41 +0200 From: Christian Bruel User-Agent: Mozilla/5.0 (X11; Linux i686 on x86_64; rv:14.0) Gecko/20120713 Thunderbird/14.0 MIME-Version: 1.0 To: "gcc-patches@gcc.gnu.org" Cc: Kaz Kojima Subject: [PATCH, SH] PR target/56995 X-Virus-Found: No Hello, While checking the register classes definitions to fix this ICE, I noticed that DF_HI_REGS seems to be always strictly equivalent to DF_REGS... Indeed, we have: /* DF_HI_REGS: Initialized TARGET_CONDITIONAL_REGISTER_USAGE.*/ { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, /* DF_REGS: */ { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, and with sh_conditional_register_usage for (regno = FIRST_FP_REG + (TARGET_LITTLE_ENDIAN != 0); regno <= LAST_FP_REG; regno += 2) SET_HARD_REG_BIT (reg_class_contents[DF_HI_REGS], regno); but the FP_REGS regno are already set ... So, Just removing DF_HI_REGS seems to fix the issue with strictly same performance results for SH4. No regressions in the testsuite for sh-sim//-m2/ sh-sim//-m2a/ sh-sim//-m2a-nofpu/ sh-sim//-m2a-single/ sh-sim//-m2a-single-only/ sh-sim//-m3/ sh-sim//-m3e/ sh-sim//-m4/ sh-sim//-m4-single/ sh-sim//-m4-single-only/ sh-sim//-m4a/ sh-sim//-m4a-single/ sh-sim//-m4a-single-only/ *[-mb,-ml] No performance regression for -m4 Hoping that I haven't missed something totally obvious with this class duplication... I'll be glad to have your feedback. The consequence of this it that find_costs_and_classes seems to be confused when two register classes are strictly equivalent. Is it plausible ? note that experimentally, I tried to reset the DF_HI_REGS class definition so it gets only the even registers set with sh_conditional_register_usage. This is also functional but gives very small worse code generation. I also simplified the mfmovd.c test to check for hard_float. Thanks a lot any other comments. Christian 2013-04-18 Christian Bruel PR target/56995 * gcc.target/sh/mfmovd.c: Add new function and check hard_float. 2013-04-18 Christian Bruel PR target/56995 * config/sh/sh.h (enum reg_class): Remove DF_HI_REGS. (REG_CLASS_NAMES): Idem. (REG_CLASS_CONTENTS): Idem. (REGCLASS_HAS_FP_REG): Idem. * config/sh/sh.c (sh_cannot_change_mode_class): Idem. (sh_conditional_register_usage): Idem. Index: gcc/testsuite/gcc.target/sh/mfmovd.c =================================================================== --- gcc/testsuite/gcc.target/sh/mfmovd.c (revision 197895) +++ gcc/testsuite/gcc.target/sh/mfmovd.c (working copy) @@ -1,8 +1,9 @@ /* Verify that we generate fmov.d instructions to move doubles when -mfmovd option is enabled. */ /* { dg-do compile { target "sh*-*-*" } } */ +/* { dg-require-effective-target hard_float } */ /* { dg-options "-mfmovd" } */ -/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a" "-m2a-single" "-m4" "-m4-single" "-m4-100" "-m4-100-single" "-m4-200" "-m4-200-single" "-m4-300" "-m4-300-single" "-m4a" "-m4a-single" } } */ +/* { dg-skip-if "" { "*-single-only" } { "" } } */ /* { dg-final { scan-assembler "fmov.d" } } */ extern double g; @@ -13,3 +14,9 @@ f (double d) g = d; } +extern float h; + +void f2 () +{ + h = g; +} Index: gcc/config/sh/sh.c =================================================================== --- gcc/config/sh/sh.c (revision 197895) +++ gcc/config/sh/sh.c (working copy) @@ -12163,7 +12163,7 @@ sh_cannot_change_mode_class (enum machine_mode fro else { if (GET_MODE_SIZE (from) < 8) - return reg_classes_intersect_p (DF_HI_REGS, rclass); + return reg_classes_intersect_p (DF_REGS, rclass); } } return false; @@ -13210,9 +13210,7 @@ sh_conditional_register_usage (void) call_really_used_regs[MACH_REG] = 0; call_really_used_regs[MACL_REG] = 0; } - for (regno = FIRST_FP_REG + (TARGET_LITTLE_ENDIAN != 0); - regno <= LAST_FP_REG; regno += 2) - SET_HARD_REG_BIT (reg_class_contents[DF_HI_REGS], regno); + if (TARGET_SHMEDIA) { for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++) Index: gcc/config/sh/sh.h =================================================================== --- gcc/config/sh/sh.h (revision 197895) +++ gcc/config/sh/sh.h (working copy) @@ -984,7 +984,6 @@ enum reg_class GENERAL_REGS, FP0_REGS, FP_REGS, - DF_HI_REGS, DF_REGS, FPSCR_REGS, GENERAL_FP_REGS, @@ -1010,7 +1009,6 @@ enum reg_class "GENERAL_REGS", \ "FP0_REGS", \ "FP_REGS", \ - "DF_HI_REGS", \ "DF_REGS", \ "FPSCR_REGS", \ "GENERAL_FP_REGS", \ @@ -1046,8 +1044,6 @@ enum reg_class { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \ /* FP_REGS: */ \ { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \ -/* DF_HI_REGS: Initialized in TARGET_CONDITIONAL_REGISTER_USAGE. */ \ - { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \ /* DF_REGS: */ \ { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \ /* FPSCR_REGS: */ \ @@ -1922,7 +1918,7 @@ struct sh_args { #define REGCLASS_HAS_FP_REG(CLASS) \ ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \ - || (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS) + || (CLASS) == DF_REGS) /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This would be so that people with slow memory systems could generate