From patchwork Wed Apr 17 09:43:11 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laxman Dewangan X-Patchwork-Id: 237191 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 6F92D2C0082 for ; Wed, 17 Apr 2013 19:48:00 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S966146Ab3DQJrh (ORCPT ); Wed, 17 Apr 2013 05:47:37 -0400 Received: from hqemgate03.nvidia.com ([216.228.121.140]:11762 "EHLO hqemgate03.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965887Ab3DQJrf (ORCPT ); Wed, 17 Apr 2013 05:47:35 -0400 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate03.nvidia.com id ; Wed, 17 Apr 2013 02:53:18 -0700 Received: from hqemhub01.nvidia.com ([172.20.12.94]) by hqnvupgp08.nvidia.com (PGP Universal service); Wed, 17 Apr 2013 02:47:23 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Wed, 17 Apr 2013 02:47:23 -0700 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server id 8.3.298.1; Wed, 17 Apr 2013 02:47:23 -0700 Received: from sc-daphne.nvidia.com (Not Verified[172.20.232.60]) by hqnvemgw01.nvidia.com with MailMarshal (v7,1,2,5326) id ; Wed, 17 Apr 2013 02:47:23 -0700 Received: from ldewangan-ubuntu.nvidia.com ([10.19.65.30]) by sc-daphne.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id r3H9lKd1013698; Wed, 17 Apr 2013 02:47:21 -0700 (PDT) From: Laxman Dewangan To: CC: , , , , , Laxman Dewangan Subject: [PATCH 1/3] regulator: palmas: clear sleep bits if not selected Date: Wed, 17 Apr 2013 15:13:11 +0530 Message-ID: <1366191793-13934-1-git-send-email-ldewangan@nvidia.com> X-Mailer: git-send-email 1.7.1.1 MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Clear the sleep/warm reset bits when it is not selected through regulator platform data. This will make sure that configuration is inline with the platform data regardless of boot/POR configuration. Signed-off-by: Laxman Dewangan Acked-by: Graeme Gregory --- drivers/regulator/palmas-regulator.c | 18 ++++++++++++------ 1 files changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/regulator/palmas-regulator.c b/drivers/regulator/palmas-regulator.c index 7c54e31..7c7992b 100644 --- a/drivers/regulator/palmas-regulator.c +++ b/drivers/regulator/palmas-regulator.c @@ -444,24 +444,26 @@ static int palmas_smps_init(struct palmas *palmas, int id, switch (id) { case PALMAS_REG_SMPS10: - if (reg_init->mode_sleep) { - reg &= ~PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK; + reg &= ~PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK; + if (reg_init->mode_sleep) reg |= reg_init->mode_sleep << PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT; - } break; default: if (reg_init->warm_reset) reg |= PALMAS_SMPS12_CTRL_WR_S; + else + reg &= ~PALMAS_SMPS12_CTRL_WR_S; if (reg_init->roof_floor) reg |= PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN; + else + reg &= ~PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN; - if (reg_init->mode_sleep) { - reg &= ~PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK; + reg &= ~PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK; + if (reg_init->mode_sleep) reg |= reg_init->mode_sleep << PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT; - } } ret = palmas_smps_write(palmas, addr, reg); @@ -507,9 +509,13 @@ static int palmas_ldo_init(struct palmas *palmas, int id, if (reg_init->warm_reset) reg |= PALMAS_LDO1_CTRL_WR_S; + else + reg &= ~PALMAS_LDO1_CTRL_WR_S; if (reg_init->mode_sleep) reg |= PALMAS_LDO1_CTRL_MODE_SLEEP; + else + reg &= ~PALMAS_LDO1_CTRL_MODE_SLEEP; ret = palmas_ldo_write(palmas, addr, reg); if (ret)