From patchwork Mon Apr 15 20:29:40 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom Warren X-Patchwork-Id: 236719 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 8F19A2C00E7 for ; Tue, 16 Apr 2013 06:35:33 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 349214A16A; Mon, 15 Apr 2013 22:35:30 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id yOYCkh6ck93B; Mon, 15 Apr 2013 22:35:30 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 03D1B4A160; Mon, 15 Apr 2013 22:35:28 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5D6834A160 for ; Mon, 15 Apr 2013 22:35:25 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id llKPLagSiWp1 for ; Mon, 15 Apr 2013 22:35:22 +0200 (CEST) X-Greylist: delayed 327 seconds by postgrey-1.27 at theia; Mon, 15 Apr 2013 22:35:21 CEST X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-qc0-f169.google.com (mail-qc0-f169.google.com [209.85.216.169]) by theia.denx.de (Postfix) with ESMTPS id 824C94A15F for ; Mon, 15 Apr 2013 22:35:20 +0200 (CEST) Received: by mail-qc0-f169.google.com with SMTP id t2so2405287qcq.14 for ; Mon, 15 Apr 2013 13:35:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer :x-nvconfidentiality; bh=Zs/TWNjEEeeR/ABlZSMDC5vKukknIce6u6JZZavjvpI=; b=bugjU7O+aP/NAJ/yxi2w8c7yhuG5lSGXy2hy7hXUhsFzgUx7y30o9gZj6bTbbXwjVc ckMfvTlWoK5zRgmCAe81TgZmDugnUuOTizo/xpJ1v92Ve4d5fygt9orPopC17rs6Io7Q dpbrsJwspVilMFJnp17poAQaHuOv4skDj/HEVCgnb6Zt6X98eRXua30WVgdkXmZkMDL8 fpJbb8urSYQtU1qAFH/jvaR5bB3lrbZQf22PKhY4C5Ttz5DgfUVPQuZBh3HdExpTKSvw 7pabXDqksD6pVXc0WevAq0b3MsroMY1ib9ctWCUh4Zn1rQU9go75xC5wU5kLO+2jFFAB hz7w== X-Received: by 10.229.57.211 with SMTP id d19mr9211320qch.121.1366057792999; Mon, 15 Apr 2013 13:29:52 -0700 (PDT) Received: from localhost.localdomain (ip68-230-103-25.ph.ph.cox.net. [68.230.103.25]) by mx.google.com with ESMTPS id m8sm34556212qav.8.2013.04.15.13.29.50 (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 15 Apr 2013 13:29:51 -0700 (PDT) From: Tom Warren To: u-boot@lists.denx.de Date: Mon, 15 Apr 2013 13:29:40 -0700 Message-Id: <1366057780-27278-1-git-send-email-twarren@nvidia.com> X-Mailer: git-send-email 1.8.1.5 X-NVConfidentiality: public Cc: swarren@nvidia.com, Tom Warren , trini@ti.com, twarren.nvidia@gmail.com Subject: [U-Boot] [PATCH v3] Tegra: T30: Beaver board support. X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Beaver is a Tegra30 board that is nearly 100% compatible w/Cardhu. Add a Beaver build so it can begin to be differentiated, if need be. Signed-off-by: Tom Warren Reviewed-by: Stephen Warren --- v2: Add MAINTAINERS and beaver.h config file v3: - Edit boards.cfg so no separate 'boards/nvidia/beaver' dir is needed - DT: Add spi-flash entry, reduce 2MB maxmem by 1MB (BootROM) - Fix MMC env offset calc to allow for larger boot partitions MAINTAINERS | 1 + board/nvidia/dts/tegra30-beaver.dts | 71 ++++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/beaver.h | 76 +++++++++++++++++++++++++++++++++++++ 4 files changed, 149 insertions(+) create mode 100644 board/nvidia/dts/tegra30-beaver.dts create mode 100644 include/configs/beaver.h diff --git a/MAINTAINERS b/MAINTAINERS index bbab5fe..643a5ac 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -994,6 +994,7 @@ Stephen Warren paz00 Tegra20 (ARM7 & A9 Dual Core) trimslice Tegra20 (ARM7 & A9 Dual Core) whistler Tegra20 (ARM7 & A9 Dual Core) + beaver Tegra30 (ARM7 & A9 Quad Core) Stephen Warren diff --git a/board/nvidia/dts/tegra30-beaver.dts b/board/nvidia/dts/tegra30-beaver.dts new file mode 100644 index 0000000..6fc3a9f --- /dev/null +++ b/board/nvidia/dts/tegra30-beaver.dts @@ -0,0 +1,71 @@ +/dts-v1/; + +#include "tegra30.dtsi" + +/ { + model = "NVIDIA Beaver"; + compatible = "nvidia,beaver", "nvidia,tegra30"; + + aliases { + i2c0 = "/i2c@7000d000"; + i2c1 = "/i2c@7000c000"; + i2c2 = "/i2c@7000c400"; + i2c3 = "/i2c@7000c500"; + i2c4 = "/i2c@7000c700"; + sdhci0 = "/sdhci@78000600"; + sdhci1 = "/sdhci@78000000"; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x7FF00000>; + }; + + i2c@7000c000 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c400 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c500 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c700 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <100000>; + }; + + spi@7000da00 { + status = "okay"; + spi-max-frequency = <25000000>; + spi-flash@1 { + compatible = "winbond,w25q32"; + reg = <1>; + spi-max-frequency = <20000000>; + }; + }; + + sdhci@78000000 { + status = "okay"; + cd-gpios = <&gpio 69 1>; /* gpio PI5 */ + wp-gpios = <&gpio 155 0>; /* gpio PT3 */ + power-gpios = <&gpio 31 0>; /* gpio PD7 */ + bus-width = <4>; + }; + + sdhci@78000600 { + status = "okay"; + bus-width = <8>; + }; +}; diff --git a/boards.cfg b/boards.cfg index f785da8..31483d6 100644 --- a/boards.cfg +++ b/boards.cfg @@ -311,6 +311,7 @@ seaboard arm armv7:arm720t seaboard nvidia ventana arm armv7:arm720t ventana nvidia tegra20 whistler arm armv7:arm720t whistler nvidia tegra20 cardhu arm armv7:arm720t cardhu nvidia tegra30 +beaver arm armv7:arm720t cardhu nvidia tegra30 dalmore arm armv7:arm720t dalmore nvidia tegra114 colibri_t20_iris arm armv7:arm720t colibri_t20_iris toradex tegra20 u8500_href arm armv7 u8500 st-ericsson u8500 diff --git a/include/configs/beaver.h b/include/configs/beaver.h new file mode 100644 index 0000000..058da4f --- /dev/null +++ b/include/configs/beaver.h @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#include "tegra30-common.h" + +/* Enable fdt support for Beaver. Flash the image in u-boot-dtb.bin */ +#define CONFIG_DEFAULT_DEVICE_TREE tegra30-beaver +#define CONFIG_OF_CONTROL +#define CONFIG_OF_SEPARATE + +/* High-level configuration options */ +#define V_PROMPT "Tegra30 (Beaver) # " +#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Beaver" + +/* Board-specific serial config */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_TEGRA_ENABLE_UARTA +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE + +#define MACH_TYPE_BEAVER 4597 /* not yet in mach-types.h */ +#define CONFIG_MACH_TYPE MACH_TYPE_BEAVER + +#define CONFIG_BOARD_EARLY_INIT_F + +/* I2C */ +#define CONFIG_TEGRA_I2C +#define CONFIG_SYS_I2C_INIT_BOARD +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_MAX_I2C_BUS TEGRA_I2C_NUM_CONTROLLERS +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_CMD_I2C + +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_TEGRA_MMC +#define CONFIG_CMD_MMC + +/* Environment in eMMC, at the end of 2nd "boot sector" */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_OFFSET ((1024 * 1024) - CONFIG_ENV_SIZE) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 + +/* SPI */ +#define CONFIG_TEGRA20_SLINK +#define CONFIG_TEGRA_SLINK_CTRLS 6 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SF_DEFAULT_SPEED 24000000 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_SIZE (4 << 20) + +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */