From patchwork Mon Apr 15 18:40:53 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 236695 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 92CF12C00E5 for ; Tue, 16 Apr 2013 05:14:30 +1000 (EST) Received: from localhost ([::1]:37122 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1URoTF-0006pf-NR for incoming@patchwork.ozlabs.org; Mon, 15 Apr 2013 14:49:41 -0400 Received: from eggs.gnu.org ([208.118.235.92]:42690) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1URoNf-0007Um-Ak for qemu-devel@nongnu.org; Mon, 15 Apr 2013 14:43:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1URoNc-0002fa-EW for qemu-devel@nongnu.org; Mon, 15 Apr 2013 14:43:55 -0400 Received: from mail-qa0-f51.google.com ([209.85.216.51]:48728) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1URoNc-0002fU-AD for qemu-devel@nongnu.org; Mon, 15 Apr 2013 14:43:52 -0400 Received: by mail-qa0-f51.google.com with SMTP id g10so616114qah.17 for ; Mon, 15 Apr 2013 11:43:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=Yw8xEoM56KLFnV2FAnF1Duojc4Xn3Wsvj1SuwR/3LD4=; b=y+oMdW5ZUkf50l5cZCqFPyec7V5UHK2coSTJATYsTnJGwVwJ7RoMwBSIzmoFkaZDsB j/TD1t5iRVDY2IypHZGewLDfxv5VfJEE7MoKKAt3bYYILDRuny7tVXmwl8I9OHCU1Io+ jtzgrsFp0aSwhZgghKfBgnJ773rOY/4LoKxYgDPjq/gj4mEoKeMFSoaEleWwcr3PKGfb 5j2c4zxCeI7P4YBtOzwJONB+CHyaak5ZS+lu3VIxW6yMvvzH2Bo0gnWdGgATxPCbfZNB AP1ris3xWXFSDdW1vUupn6nJgUpBBpRKo7+FdXDU8soJTjeLs1C6+Xk87lr6VGVqAhXP IjwA== X-Received: by 10.49.49.72 with SMTP id s8mr27006844qen.54.1366051431891; Mon, 15 Apr 2013 11:43:51 -0700 (PDT) Received: from pebble.com (214.Red-217-126-56.staticIP.rima-tde.net. [217.126.56.214]) by mx.google.com with ESMTPS id g6sm33990707qav.6.2013.04.15.11.43.43 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 15 Apr 2013 11:43:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 15 Apr 2013 20:40:53 +0200 Message-Id: <1366051272-12979-15-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1366051272-12979-1-git-send-email-rth@twiddle.net> References: <1366051272-12979-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 209.85.216.51 Cc: av1474@comtv.ru, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH v5 14/33] tcg-ppc64: Improve and_i32 with constant X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Use RLWINM Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- tcg/ppc64/tcg-target.c | 50 +++++++++++++++++++++++++++++++++++++++++++++++++- tcg/ppc64/tcg-target.h | 6 ++++-- 2 files changed, 53 insertions(+), 3 deletions(-) diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index c8cae72..1b0563f 100644 --- a/tcg/ppc64/tcg-target.c +++ b/tcg/ppc64/tcg-target.c @@ -527,6 +527,48 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, } } +static inline bool mask_operand(uint32_t c, int *mb, int *me) +{ + uint32_t lsb, test; + + /* Accept a bit pattern like: + 0....01....1 + 1....10....0 + 0..01..10..0 + Keep track of the transitions. */ + if (c == 0 || c == -1) { + return false; + } + test = c; + lsb = test & -test; + test += lsb; + if (test & (test - 1)) { + return false; + } + + *me = clz32(lsb); + *mb = test ? clz32(test & -test) + 1 : 0; + return true; +} + +static void tcg_out_andi32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c) +{ + int mb, me; + + if ((c & 0xffff) == c) { + tcg_out32(s, ANDI | SAI(src, dst, c)); + return; + } else if ((c & 0xffff0000) == c) { + tcg_out32(s, ANDIS | SAI(src, dst, c >> 16)); + return; + } else if (mask_operand(c, &mb, &me)) { + tcg_out_rlw(s, RLWINM, dst, src, 0, mb, me); + } else { + tcg_out_movi(s, TCG_TYPE_I32, 0, c); + tcg_out32(s, AND | SAB(src, dst, 0)); + } +} + static void tcg_out_zori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c, int op_lo, int op_hi) { @@ -1352,9 +1394,15 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args, } break; - case INDEX_op_and_i64: case INDEX_op_and_i32: if (const_args[2]) { + tcg_out_andi32(s, args[0], args[1], args[2]); + } else { + tcg_out32(s, AND | SAB(args[1], args[0], args[2])); + } + break; + case INDEX_op_and_i64: + if (const_args[2]) { if ((args[2] & 0xffff) == args[2]) { tcg_out32(s, ANDI | SAI(args[1], args[0], args[2])); } else if ((args[2] & 0xffff0000) == args[2]) { diff --git a/tcg/ppc64/tcg-target.h b/tcg/ppc64/tcg-target.h index aa6a0f0..f1c3067 100644 --- a/tcg/ppc64/tcg-target.h +++ b/tcg/ppc64/tcg-target.h @@ -67,13 +67,15 @@ typedef enum { #define TCG_TARGET_STACK_ALIGN 16 #define TCG_TARGET_CALL_STACK_OFFSET 48 +/* optional instructions automatically implemented */ +#define TCG_TARGET_HAS_ext8u_i32 0 /* andi */ +#define TCG_TARGET_HAS_ext16u_i32 0 + /* optional instructions */ #define TCG_TARGET_HAS_div_i32 1 #define TCG_TARGET_HAS_rot_i32 0 #define TCG_TARGET_HAS_ext8s_i32 1 #define TCG_TARGET_HAS_ext16s_i32 1 -#define TCG_TARGET_HAS_ext8u_i32 0 -#define TCG_TARGET_HAS_ext16u_i32 0 #define TCG_TARGET_HAS_bswap16_i32 0 #define TCG_TARGET_HAS_bswap32_i32 0 #define TCG_TARGET_HAS_not_i32 1