From patchwork Mon Apr 15 18:41:12 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 236686 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 1BD3C2C00E6 for ; Tue, 16 Apr 2013 04:57:37 +1000 (EST) Received: from localhost ([::1]:55124 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1URoat-0000kW-Dk for incoming@patchwork.ozlabs.org; Mon, 15 Apr 2013 14:57:35 -0400 Received: from eggs.gnu.org ([208.118.235.92]:43395) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1URoPl-00024j-Nn for qemu-devel@nongnu.org; Mon, 15 Apr 2013 14:46:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1URoPi-0003iX-KD for qemu-devel@nongnu.org; Mon, 15 Apr 2013 14:46:05 -0400 Received: from mail-qa0-f53.google.com ([209.85.216.53]:55098) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1URoPi-0003hM-F3 for qemu-devel@nongnu.org; Mon, 15 Apr 2013 14:46:02 -0400 Received: by mail-qa0-f53.google.com with SMTP id p6so725185qad.19 for ; Mon, 15 Apr 2013 11:46:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=4tHV/2funNEW7eZ9EZcrqj3ioxk+NfPGB1d+KDMhf64=; b=pjlcmnTBE46M9Ll6SpkajR1Ct+nKOQwL5wrDF5IoIuH693csQwwlJdtzzIF3ju8o6U DjSAVHERrn+Q2w+ZI5VrHVGd80L/otsW9GXM7oG/mskSNizjKjO5bocb9brn4VhTvjj1 CuwrFYIRCyc6i/iu5e6Inl+WNIhd4KL7Phlv8FCT1ceQe64dEJ41OwgOCgPZvbRZ2kY0 c8GVLOzHISY294JwDKjGl25zcrRSiAvuXJ0Y20D+InstXGyMJtyIu3Tn+O5k36FqPayP KP22gTYVmjtYPgsDcPhMJcjqGGmLUUgb0g7hutW+BsqIsirI16CcZrYUtux5gPgIJ+SI Ql7w== X-Received: by 10.49.4.129 with SMTP id k1mr27146805qek.18.1366051562037; Mon, 15 Apr 2013 11:46:02 -0700 (PDT) Received: from pebble.com (214.Red-217-126-56.staticIP.rima-tde.net. [217.126.56.214]) by mx.google.com with ESMTPS id g6sm33990707qav.6.2013.04.15.11.45.56 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 15 Apr 2013 11:46:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 15 Apr 2013 20:41:12 +0200 Message-Id: <1366051272-12979-34-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1366051272-12979-1-git-send-email-rth@twiddle.net> References: <1366051272-12979-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 209.85.216.53 Cc: av1474@comtv.ru, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH v5 33/33] tcg-ppc64: Handle deposit of zero X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The TCG optimizer does great work when inserting constants, being able to fold the open-coded deposit expansion to just an AND or an OR. Avoid a bit the regression caused by having the deposit opcode by expanding deposit of zero as an AND. Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- tcg/ppc64/tcg-target.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index 0f33583..0fcf2b5 100644 --- a/tcg/ppc64/tcg-target.c +++ b/tcg/ppc64/tcg-target.c @@ -1928,12 +1928,22 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args, break; case INDEX_op_deposit_i32: - tcg_out_rlw(s, RLWIMI, args[0], args[2], args[3], - 32 - args[3] - args[4], 31 - args[3]); + if (const_args[2]) { + uint32_t mask = ((2u << (args[4] - 1)) - 1) << args[3]; + tcg_out_andi32(s, args[0], args[0], ~mask); + } else { + tcg_out_rlw(s, RLWIMI, args[0], args[2], args[3], + 32 - args[3] - args[4], 31 - args[3]); + } break; case INDEX_op_deposit_i64: - tcg_out_rld(s, RLDIMI, args[0], args[2], args[3], - 64 - args[3] - args[4]); + if (const_args[2]) { + uint64_t mask = ((2ull << (args[4] - 1)) - 1) << args[3]; + tcg_out_andi64(s, args[0], args[0], ~mask); + } else { + tcg_out_rld(s, RLDIMI, args[0], args[2], args[3], + 64 - args[3] - args[4]); + } break; case INDEX_op_movcond_i32: @@ -2136,8 +2146,8 @@ static const TCGTargetOpDef ppc_op_defs[] = { { INDEX_op_bswap32_i64, { "r", "r" } }, { INDEX_op_bswap64_i64, { "r", "r" } }, - { INDEX_op_deposit_i32, { "r", "0", "r" } }, - { INDEX_op_deposit_i64, { "r", "0", "r" } }, + { INDEX_op_deposit_i32, { "r", "0", "rZ" } }, + { INDEX_op_deposit_i64, { "r", "0", "rZ" } }, { INDEX_op_add2_i64, { "r", "r", "r", "rI", "r", "rZM" } }, { INDEX_op_sub2_i64, { "r", "r", "rI", "r", "rZM", "r" } },