From patchwork Mon Apr 15 18:40:49 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 236674 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 202562C00F9 for ; Tue, 16 Apr 2013 04:48:26 +1000 (EST) Received: from localhost ([::1]:33217 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1URoS0-0004Sy-Ch for incoming@patchwork.ozlabs.org; Mon, 15 Apr 2013 14:48:24 -0400 Received: from eggs.gnu.org ([208.118.235.92]:42557) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1URoN7-0006SB-D5 for qemu-devel@nongnu.org; Mon, 15 Apr 2013 14:43:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1URoN4-0002Zc-F4 for qemu-devel@nongnu.org; Mon, 15 Apr 2013 14:43:21 -0400 Received: from mail-qe0-f45.google.com ([209.85.128.45]:34112) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1URoN4-0002ZW-Aj for qemu-devel@nongnu.org; Mon, 15 Apr 2013 14:43:18 -0400 Received: by mail-qe0-f45.google.com with SMTP id 1so2859443qee.18 for ; Mon, 15 Apr 2013 11:43:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=YtreoVsg3mWFge+EMK6h17ye59eQet1u3lD1xG+8NSY=; b=guQM/JuxT7ikKEYa/jwl2tuhiTMEfk4T4npm1IognIxvBQKEfyqzoOLooyQN4oOqCC 0S0jb/KS90mUJlYWE1PnubKn2mWCKE6M9Vh24RDi/QZBsKzl0+jjGZuqnzo1YAW77jTd glgw4lKaCR6hQfDZa0zd4MX2vErwkkWzxB6UCgIsVz7yV8amRyrDRsvKgFU3/XZhD2YR l9uGHRqv46a+fKotACn3ZLjiZr7VILsuoo3IBB0wdVPhfctpgGrQBDck/mUfUSngDK4+ mVOJRmTfFHGAWziK7zv9x4XhtXfs2N+8vIwXL4DlN+vvaa4sYZJTtECO+o7I0/pXrpNe oPXA== X-Received: by 10.224.41.200 with SMTP id p8mr390154qae.99.1366051398003; Mon, 15 Apr 2013 11:43:18 -0700 (PDT) Received: from pebble.com (214.Red-217-126-56.staticIP.rima-tde.net. [217.126.56.214]) by mx.google.com with ESMTPS id g6sm33990707qav.6.2013.04.15.11.43.12 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 15 Apr 2013 11:43:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 15 Apr 2013 20:40:49 +0200 Message-Id: <1366051272-12979-11-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1366051272-12979-1-git-send-email-rth@twiddle.net> References: <1366051272-12979-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 209.85.128.45 Cc: av1474@comtv.ru, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH v5 10/33] tcg-ppc64: Rearrange integer constant constraints X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org We'll need a zero, and Z makes more sense for that. Make sure we have a full compliment of signed and unsigned 16 and 32-bit tests. Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- tcg/ppc64/tcg-target.c | 43 +++++++++++++++++++++++++++++++++---------- 1 file changed, 33 insertions(+), 10 deletions(-) diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index c6ff75b..6ba09ab 100644 --- a/tcg/ppc64/tcg-target.c +++ b/tcg/ppc64/tcg-target.c @@ -22,7 +22,11 @@ * THE SOFTWARE. */ -#define TCG_CT_CONST_U32 0x100 +#define TCG_CT_CONST_S16 0x100 +#define TCG_CT_CONST_U16 0x200 +#define TCG_CT_CONST_S32 0x400 +#define TCG_CT_CONST_U32 0x800 +#define TCG_CT_CONST_ZERO 0x1000 static uint8_t *tb_ret_addr; @@ -242,9 +246,21 @@ static int target_parse_constraint (TCGArgConstraint *ct, const char **pct_str) tcg_regset_reset_reg (ct->u.regs, TCG_REG_R6); #endif break; - case 'Z': + case 'I': + ct->ct |= TCG_CT_CONST_S16; + break; + case 'J': + ct->ct |= TCG_CT_CONST_U16; + break; + case 'T': + ct->ct |= TCG_CT_CONST_S32; + break; + case 'U': ct->ct |= TCG_CT_CONST_U32; break; + case 'Z': + ct->ct |= TCG_CT_CONST_ZERO; + break; default: return -1; } @@ -257,13 +273,20 @@ static int target_parse_constraint (TCGArgConstraint *ct, const char **pct_str) static int tcg_target_const_match (tcg_target_long val, const TCGArgConstraint *arg_ct) { - int ct; - - ct = arg_ct->ct; - if (ct & TCG_CT_CONST) + int ct = arg_ct->ct; + if (ct & TCG_CT_CONST) { + return 1; + } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) { + return 1; + } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) { return 1; - else if ((ct & TCG_CT_CONST_U32) && (val == (uint32_t) val)) + } else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) { return 1; + } else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) { + return 1; + } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) { + return 1; + } return 0; } @@ -1613,9 +1636,9 @@ static const TCGTargetOpDef ppc_op_defs[] = { { INDEX_op_add_i64, { "r", "r", "ri" } }, { INDEX_op_sub_i64, { "r", "r", "ri" } }, - { INDEX_op_and_i64, { "r", "r", "rZ" } }, - { INDEX_op_or_i64, { "r", "r", "rZ" } }, - { INDEX_op_xor_i64, { "r", "r", "rZ" } }, + { INDEX_op_and_i64, { "r", "r", "rU" } }, + { INDEX_op_or_i64, { "r", "r", "rU" } }, + { INDEX_op_xor_i64, { "r", "r", "rU" } }, { INDEX_op_shl_i64, { "r", "r", "ri" } }, { INDEX_op_shr_i64, { "r", "r", "ri" } },