From patchwork Mon Apr 15 18:40:39 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 236666 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 2D5D72C00EF for ; Tue, 16 Apr 2013 04:42:46 +1000 (EST) Received: from localhost ([::1]:48642 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1URoMW-0004e2-AN for incoming@patchwork.ozlabs.org; Mon, 15 Apr 2013 14:42:44 -0400 Received: from eggs.gnu.org ([208.118.235.92]:42193) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1URoM6-0004at-9k for qemu-devel@nongnu.org; Mon, 15 Apr 2013 14:42:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1URoM3-0002AQ-BZ for qemu-devel@nongnu.org; Mon, 15 Apr 2013 14:42:18 -0400 Received: from mail-qc0-x235.google.com ([2607:f8b0:400d:c01::235]:42790) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1URoM3-0002AC-7X for qemu-devel@nongnu.org; Mon, 15 Apr 2013 14:42:15 -0400 Received: by mail-qc0-f181.google.com with SMTP id a22so798381qcs.26 for ; Mon, 15 Apr 2013 11:42:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer; bh=UEmGvJoKx9GYUELxMaP5OTKDWogOvKa7fCej1po2ldA=; b=danKFGDXiuY9NEySiG6NF8d3MOcRJIIyxtUfN+ZUDZ/sqk4kEeHOTIHpRJYqFuW0wN BnSAtQBUqAQz2ffLfT8Hf9+xBt+bd2VwK3ACnulw+sO5GwZnPdk08MZFudJ3NCD9TazA 4VEGJ95I2SycxXsOMiifG+Ptfeq4kIc8xH4AH2rxy0RWZIijJDeNXrCdHSxTZ1C9P7rt YClC4P+UaYhwXxXe7oQgzwradv1zg5JbbdfM/Q6qUri3KgvDICsnZ9BqjltOUyLer1n8 k1Awyh/Va3nlfAarDytUTJnhK0nukhtC6Df1MkbbvbY1j/JqnFu9wdJ0/5//D82btACA OJyQ== X-Received: by 10.229.115.204 with SMTP id j12mr5809403qcq.119.1366051333947; Mon, 15 Apr 2013 11:42:13 -0700 (PDT) Received: from pebble.com (214.Red-217-126-56.staticIP.rima-tde.net. [217.126.56.214]) by mx.google.com with ESMTPS id g6sm33990707qav.6.2013.04.15.11.42.07 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 15 Apr 2013 11:42:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 15 Apr 2013 20:40:39 +0200 Message-Id: <1366051272-12979-1-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.1.4 X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400d:c01::235 Cc: av1474@comtv.ru, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH v5 00/33] Modernize tcg/ppc64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Changes v4-v5: * Use TCG_REG_R0 in the bswap patch, feedback from Aurelien. * Rebased to master. The following changes since commit 0ca5aa4f4c4a8bcc73988dd52a536241d35e5223: qemu-char: another io_add_watch_poll fix (2013-04-15 10:22:05 -0500) are available in the git repository at: git://github.com/rth7680/qemu.git tcg-ppc64 for you to fetch changes up to 39dc85b98561ea3de2b029f43a3a2db95c57afa3: tcg-ppc64: Handle deposit of zero (2013-04-15 20:09:55 +0200) r~ Richard Henderson (33): disas: Disassemble all ppc insns for the host tcg-ppc64: Use TCGReg everywhere tcg-ppc64: Introduce and use tcg_out_rlw tcg-ppc64: Introduce and use tcg_out_ext32u tcg-ppc64: Introduce and use tcg_out_shli64 tcg-ppc64: Introduce and use tcg_out_shri64 tcg-ppc64: Introduce and use TAI and SAI tcg-ppc64: Fix setcond_i32 tcg-ppc64: Cleanup tcg_out_movi tcg-ppc64: Rearrange integer constant constraints tcg-ppc64: Improve constant add and sub ops. tcg-ppc64: Allow constant first argument to sub tcg-ppc64: Tidy or and xor patterns. tcg-ppc64: Improve and_i32 with constant tcg-ppc64: Improve and_i64 with constant tcg-ppc64: Use automatic implementation of ext32u_i64 tcg-ppc64: Streamline qemu_ld/st insn selection tcg-ppc64: Implement rotates tcg-ppc64: Implement bswap16 and bswap32 tcg-ppc64: Implement bswap64 tcg-ppc64: Implement compound logicals tcg-ppc64: Handle constant inputs for some compound logicals tcg-ppc64: Implement deposit tcg-ppc64: Use I constraint for mul tcg-ppc64: Use TCGType throughout compares tcg-ppc64: Cleanup i32 constants to tcg_out_cmp tcg-ppc64: Use MFOCRF instead of MFCR tcg-ppc64: Use ISEL for setcond tcg-ppc64: Implement movcond tcg-ppc64: Use getauxval for ISA detection tcg-ppc64: Implement add2/sub2_i64 tcg-ppc64: Implement mulu2/muls2_i64 tcg-ppc64: Handle deposit of zero configure | 18 + disas.c | 1 + tcg/ppc64/tcg-target.c | 1344 +++++++++++++++++++++++++++++++++--------------- tcg/ppc64/tcg-target.h | 62 +-- 4 files changed, 968 insertions(+), 457 deletions(-)