Patchwork [resend,2/2] clk: tegra: add ac97 controller clock

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Submitter Lucas Stach
Date April 15, 2013, 7:31 a.m.
Message ID <1366011105-2351-2-git-send-email-dev@lynxeye.de>
Download mbox | patch
Permalink /patch/236508/
State Accepted, archived
Headers show

Comments

Lucas Stach - April 15, 2013, 7:31 a.m.
AC97 controller clock is hardwired to pll_a_out0.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 drivers/clk/tegra/clk-tegra20.c | 8 ++++++++
 1 file changed, 8 insertions(+)
Peter De Schrijver - April 15, 2013, 11:03 a.m.
On Mon, Apr 15, 2013 at 09:31:45AM +0200, Lucas Stach wrote:
> AC97 controller clock is hardwired to pll_a_out0.
> 

Prashant, did you just forget to add this clock?

> Signed-off-by: Lucas Stach <dev@lynxeye.de>
> ---
>  drivers/clk/tegra/clk-tegra20.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
> index a73278f..bbcca91 100644
> --- a/drivers/clk/tegra/clk-tegra20.c
> +++ b/drivers/clk/tegra/clk-tegra20.c
> @@ -897,6 +897,14 @@ static void __init tegra20_periph_clk_init(void)
>  	struct clk *clk;
>  	int i;
>  
> +	/* ac97 */
> +	clk = tegra_clk_register_periph_gate("ac97", "pll_a_out0",
> +				    TEGRA_PERIPH_ON_APB,
> +				    clk_base, 0, 3, &periph_l_regs,
> +				    periph_clk_enb_refcnt);
> +	clk_register_clkdev(clk, NULL, "tegra20-ac97");
> +	clks[ac97] = clk;
> +
>  	/* apbdma */
>  	clk = tegra_clk_register_periph_gate("apbdma", "pclk", 0, clk_base,
>  				    0, 34, &periph_h_regs,

Otherwise:

Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>

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Prashant Gaikwad - April 17, 2013, 12:17 p.m.
On Monday 15 April 2013 01:01 PM, Lucas Stach wrote:
> AC97 controller clock is hardwired to pll_a_out0.
>
> Signed-off-by: Lucas Stach <dev@lynxeye.de>
> ---

It was not there in previous implementation neither do we implement it 
in our downstream kernel.

Lucas, are you using this clock anywhere?

Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>

>   drivers/clk/tegra/clk-tegra20.c | 8 ++++++++
>   1 file changed, 8 insertions(+)
>
> diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
> index a73278f..bbcca91 100644
> --- a/drivers/clk/tegra/clk-tegra20.c
> +++ b/drivers/clk/tegra/clk-tegra20.c
> @@ -897,6 +897,14 @@ static void __init tegra20_periph_clk_init(void)
>   	struct clk *clk;
>   	int i;
>   
> +	/* ac97 */
> +	clk = tegra_clk_register_periph_gate("ac97", "pll_a_out0",
> +				    TEGRA_PERIPH_ON_APB,
> +				    clk_base, 0, 3, &periph_l_regs,
> +				    periph_clk_enb_refcnt);
> +	clk_register_clkdev(clk, NULL, "tegra20-ac97");
> +	clks[ac97] = clk;
> +
>   	/* apbdma */
>   	clk = tegra_clk_register_periph_gate("apbdma", "pclk", 0, clk_base,
>   				    0, 34, &periph_h_regs,

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Stephen Warren - April 17, 2013, 3:11 p.m.
On 04/17/2013 06:17 AM, Prashant Gaikwad wrote:
> On Monday 15 April 2013 01:01 PM, Lucas Stach wrote:
>> AC97 controller clock is hardwired to pll_a_out0.
>>
>> Signed-off-by: Lucas Stach <dev@lynxeye.de>
>> ---
> 
> It was not there in previous implementation neither do we implement it
> in our downstream kernel.
> 
> Lucas, are you using this clock anywhere?

Yes, there's an AC'97 driver upstream now, which Lucas wrote. It's used
on the Colibri T20 board.
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Patch

diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index a73278f..bbcca91 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -897,6 +897,14 @@  static void __init tegra20_periph_clk_init(void)
 	struct clk *clk;
 	int i;
 
+	/* ac97 */
+	clk = tegra_clk_register_periph_gate("ac97", "pll_a_out0",
+				    TEGRA_PERIPH_ON_APB,
+				    clk_base, 0, 3, &periph_l_regs,
+				    periph_clk_enb_refcnt);
+	clk_register_clkdev(clk, NULL, "tegra20-ac97");
+	clks[ac97] = clk;
+
 	/* apbdma */
 	clk = tegra_clk_register_periph_gate("apbdma", "pclk", 0, clk_base,
 				    0, 34, &periph_h_regs,