From patchwork Sun Apr 14 08:39:59 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Botcazou X-Patchwork-Id: 236419 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "localhost", Issuer "www.qmailtoaster.com" (not verified)) by ozlabs.org (Postfix) with ESMTPS id E6CB32C0099 for ; Sun, 14 Apr 2013 18:42:14 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type :content-transfer-encoding; q=dns; s=default; b=G/y8F9jHjoCfRqOf MvGIvT8NKyf/Ddr2oApCmp5gJGZ7l/y57nji4X1HpWg4xPRc0ZmQAvVrLf+h2wV6 bTrYg6YolBiy9VgMVjFegf8DAFmEhDvx8Z9TRwQeaetd6CcRO5vEamxZnGgGblPT 1MI2bMzIzoTGRIwNq2MbUcOqeUc= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type :content-transfer-encoding; s=default; bh=3S39TIqB2cES1EZOJREpMm 3Ou2A=; b=fqmCIfezxc1ZD67esDGCqajvWSmtly5hFyNDtMzn8r2A8UDWaaIlJy e6jR8U1Nd+jGAvMLIXXQH8XC9ve1PpKgfEVWKH8snNJTGk9KNrCNBLnrWFWkG/L6 YDEQ0QQO8ZxZDr4x/d37wOxzv7jLxZQZF0Z2MLvphBNNct2OoBp04= Received: (qmail 15788 invoked by alias); 14 Apr 2013 08:42:07 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 15773 invoked by uid 89); 14 Apr 2013 08:42:07 -0000 X-Spam-SWARE-Status: No, score=-2.2 required=5.0 tests=AWL, BAYES_00 autolearn=ham version=3.3.1 Received: from mel.act-europe.fr (HELO mel.act-europe.fr) (194.98.77.210) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Sun, 14 Apr 2013 08:42:06 +0000 Received: from localhost (localhost [127.0.0.1]) by filtered-smtp.eu.adacore.com (Postfix) with ESMTP id 19C2A290016; Sun, 14 Apr 2013 10:42:04 +0200 (CEST) Received: from mel.act-europe.fr ([127.0.0.1]) by localhost (smtp.eu.adacore.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id E3FpM99G60WW; Sun, 14 Apr 2013 10:42:04 +0200 (CEST) Received: from polaris.localnet (bon31-6-88-161-99-133.fbx.proxad.net [88.161.99.133]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mel.act-europe.fr (Postfix) with ESMTP id 438B329000E; Sun, 14 Apr 2013 10:42:02 +0200 (CEST) From: Eric Botcazou To: gcc-patches@gcc.gnu.org Cc: David Miller , Jakub Jelinek Subject: [SPARC] Fix PR target/56890 Date: Sun, 14 Apr 2013 10:39:59 +0200 Message-ID: <3344061.A5Rjyamnnq@polaris> User-Agent: KMail/4.7.2 (Linux/3.1.10-1.19-desktop; KDE/4.7.2; x86_64; ; ) MIME-Version: 1.0 X-Virus-Found: No To my great surprise, this PR shows that the SPARC back-end allows QImode and HImode values to live in FP registers, but can neither load nor move them. This can result in an unrecognizable move insn between FP registers or an illegal fdtox instruction in 64-bit mode as shown by the submitted testcases. The attached patch changes that and yields no regressions both in 32-bit and 64-bit modes. Any objections to applying it to all active branches? 2013-04-14 Eric Botcazou PR target/56890 * config/sparc/sparc.c (enum sparc_mode_class): Add H_MODE value. (S_MODES): Set H_MODE bit. (SF_MODES): Set only S_MODE and SF_MODE bits. (DF_MODES): Set SF_MODES and only D_MODE and DF_MODE bits. (sparc_init_modes) : Set H_MODE bit for sub-word modes. : Do not set SF_MODE for sub-word modes. : Likewise. 2013-04-14 Eric Botcazou * gcc.dg/pr56890-1.c: New test. * gcc.dg/pr56890-2.c: Likewise. Index: config/sparc/sparc.c =================================================================== --- config/sparc/sparc.c (revision 197926) +++ config/sparc/sparc.c (working copy) @@ -4467,13 +4467,14 @@ mem_min_alignment (rtx mem, int desired) mapped into one sparc_mode_class mode. */ enum sparc_mode_class { - S_MODE, D_MODE, T_MODE, O_MODE, + H_MODE, S_MODE, D_MODE, T_MODE, O_MODE, SF_MODE, DF_MODE, TF_MODE, OF_MODE, CC_MODE, CCFP_MODE }; /* Modes for single-word and smaller quantities. */ -#define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE)) +#define S_MODES \ + ((1 << (int) H_MODE) | (1 << (int) S_MODE) | (1 << (int) SF_MODE)) /* Modes for double-word and smaller quantities. */ #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE)) @@ -4484,13 +4485,11 @@ enum sparc_mode_class { /* Modes for 8-word and smaller quantities. */ #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE)) -/* Modes for single-float quantities. We must allow any single word or - smaller quantity. This is because the fix/float conversion instructions - take integer inputs/outputs from the float registers. */ -#define SF_MODES (S_MODES) +/* Modes for single-float quantities. */ +#define SF_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE)) /* Modes for double-float and smaller quantities. */ -#define DF_MODES (D_MODES) +#define DF_MODES (SF_MODES | (1 << (int) D_MODE) | (1 << DF_MODE)) /* Modes for quad-float and smaller quantities. */ #define TF_MODES (DF_MODES | (1 << (int) TF_MODE)) @@ -4586,7 +4585,9 @@ sparc_init_modes (void) case MODE_INT: case MODE_PARTIAL_INT: case MODE_COMPLEX_INT: - if (GET_MODE_SIZE (i) <= 4) + if (GET_MODE_SIZE (i) < 4) + sparc_mode_class[i] = 1 << (int) H_MODE; + else if (GET_MODE_SIZE (i) == 4) sparc_mode_class[i] = 1 << (int) S_MODE; else if (GET_MODE_SIZE (i) == 8) sparc_mode_class[i] = 1 << (int) D_MODE; @@ -4598,14 +4599,16 @@ sparc_init_modes (void) sparc_mode_class[i] = 0; break; case MODE_VECTOR_INT: - if (GET_MODE_SIZE (i) <= 4) - sparc_mode_class[i] = 1 << (int)SF_MODE; + if (GET_MODE_SIZE (i) == 4) + sparc_mode_class[i] = 1 << (int) SF_MODE; else if (GET_MODE_SIZE (i) == 8) - sparc_mode_class[i] = 1 << (int)DF_MODE; + sparc_mode_class[i] = 1 << (int) DF_MODE; + else + sparc_mode_class[i] = 0; break; case MODE_FLOAT: case MODE_COMPLEX_FLOAT: - if (GET_MODE_SIZE (i) <= 4) + if (GET_MODE_SIZE (i) == 4) sparc_mode_class[i] = 1 << (int) SF_MODE; else if (GET_MODE_SIZE (i) == 8) sparc_mode_class[i] = 1 << (int) DF_MODE;