Patchwork [AArch64] Compare instruction in shift_extend mode

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Submitter Hurugalawadi, Naveen
Date April 12, 2013, 11:44 a.m.
Message ID <533cf85bfb7f48bca2fd6baeb2336147@SN2PR07MB029.namprd07.prod.outlook.com>
Download mbox | patch
Permalink /patch/236056/
State New
Headers show

Comments

Hurugalawadi, Naveen - April 12, 2013, 11:44 a.m.
Hi,

Please find attached the patch that implements compare instruction in
shift_extend mode for aarch64 target.

Testcase has been added for compare instructions.

Please review the same and let me know if there should be any 
modifications in the patch.
 
Build and tested on aarch64-thunder-elf (using Cavium's internal
simulator). No new regressions.

Thanks,
Naveen

gcc/

2013-04-12   Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>

	* config/aarch64/aarch64.md 
	(*cmp_swp_<optab><ALLX:mode>_shft_<GPI:mode>): New pattern.

gcc/testsuite/

2013-04-12   Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>

	* gcc.target/aarch64/cmp.c: New.
Richard Earnshaw - April 12, 2013, 1:11 p.m.
On 12/04/13 12:44, Hurugalawadi, Naveen wrote:
> Hi,
>
> Please find attached the patch that implements compare instruction in
> shift_extend mode for aarch64 target.
>
> Testcase has been added for compare instructions.
>
> Please review the same and let me know if there should be any
> modifications in the patch.
>
> Build and tested on aarch64-thunder-elf (using Cavium's internal
> simulator). No new regressions.
>
> Thanks,
> Naveen
>
> gcc/
>
> 2013-04-12   Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>
>
> 	* config/aarch64/aarch64.md
> 	(*cmp_swp_<optab><ALLX:mode>_shft_<GPI:mode>): New pattern.
>
> gcc/testsuite/
>
> 2013-04-12   Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>
>
> 	* gcc.target/aarch64/cmp.c: New.
>
>

> --- gcc/testsuite/gcc.target/aarch64/cmp.c	1970-01-01 05:30:00.000000000 +0530
> +++ gcc/testsuite/gcc.target/aarch64/cmp.c	2013-04-12 16:36:57.232943520 +0530
> @@ -0,0 +1,138 @@
> +/* { dg-do run } */
> +/* { dg-options "-O2 --save-temps" } */
> +
> +extern void abort (void);
> +
> +int
> +cmp_si_test1 (int a, int b, int c)
> +{
> +  /* { dg-final { scan-assembler "cmp\tw\[0-9\]+, w\[0-9\]+" } } */
> +  if (a > b)
> +    return a + c;
> +  else
> +    return a + b + c;
> +}
> +
> +int
> +cmp_si_test2 (int a, int b, int c)
> +{
> +  /* { dg-final { scan-assembler "cmp\tw\[0-9\]+, w\[0-9\]+, asr 3" } } */
> +  if ((a >> 3) > b)
> +    return a + c;
> +  else
> +    return a + b + c;
> +}
> +
> +typedef long long s64;
> +
> +s64
> +cmp_di_test1 (s64 a, s64 b, s64 c)
> +{
> +  /* { dg-final { scan-assembler "cmp\tx\[0-9\]+, x\[0-9\]+" } } */
> +  if (a > b)
> +    return a + c;
> +  else
> +    return a + b + c;
> +}
> +
> +s64
> +cmp_di_test2 (s64 a, s64 b, s64 c)
> +{
> +  /* { dg-final { scan-assembler "cmp\tx\[0-9\]+, x\[0-9\]+, asr 3" } } */
> +  if ((a >> 3) > b)
> +    return a + c;
> +  else
> +    return a + b + c;
> +}
> +
> +int
> +cmp_di_test3 (int a, s64 b, s64 c)
> +{
> +  /* { dg-final { scan-assembler "cmp\tx\[0-9\]+, x\[0-9\]+, sxtw" } } */
> +  if (a > b)
> +    return a + c;
> +  else
> +    return a + b + c;
> +}
> +
> +int
> +cmp_di_test4 (int a, s64 b, s64 c)
> +{
> +  /* { dg-final { scan-assembler "cmp\tx\[0-9\]+, x\[0-9\]+, sxtw 3" } } */
> +  if (((s64)a << 3) > b)
> +    return a + c;
> +  else
> +    return a + b + c;
> +}
> +

Same issue as my previous reply applies here.

R.

Patch

--- gcc/config/aarch64/aarch64.md	2013-04-12 10:03:11.924990662 +0530
+++ gcc/config/aarch64/aarch64.md	2013-04-12 16:39:18.284943238 +0530
@@ -2205,6 +2205,18 @@ 
    (set_attr "mode" "<GPI:MODE>")]
 )
 
+(define_insn "*cmp_swp_<optab><ALLX:mode>_shft_<GPI:mode>"
+  [(set (reg:CC_SWP CC_REGNUM)
+	(compare:CC_SWP (ashift:GPI
+			 (ANY_EXTEND:GPI
+			  (match_operand:ALLX 0 "register_operand" "r"))
+			 (match_operand:QI 1 "aarch64_shift_imm_<mode>" "n"))
+	(match_operand:GPI 2 "register_operand" "r")))]
+  ""
+  "cmp\\t%<GPI:w>2, %<GPI:w>0, <su>xt<ALLX:size> %1"
+  [(set_attr "v8type" "alus_ext")
+   (set_attr "mode" "<GPI:MODE>")]
+)
 
 ;; -------------------------------------------------------------------
 ;; Store-flag and conditional select insns
--- gcc/testsuite/gcc.target/aarch64/cmp.c	1970-01-01 05:30:00.000000000 +0530
+++ gcc/testsuite/gcc.target/aarch64/cmp.c	2013-04-12 16:36:57.232943520 +0530
@@ -0,0 +1,138 @@ 
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps" } */
+
+extern void abort (void);
+
+int
+cmp_si_test1 (int a, int b, int c)
+{
+  /* { dg-final { scan-assembler "cmp\tw\[0-9\]+, w\[0-9\]+" } } */
+  if (a > b)
+    return a + c;
+  else
+    return a + b + c;
+}
+
+int
+cmp_si_test2 (int a, int b, int c)
+{
+  /* { dg-final { scan-assembler "cmp\tw\[0-9\]+, w\[0-9\]+, asr 3" } } */
+  if ((a >> 3) > b)
+    return a + c;
+  else
+    return a + b + c;
+}
+
+typedef long long s64;
+
+s64
+cmp_di_test1 (s64 a, s64 b, s64 c)
+{
+  /* { dg-final { scan-assembler "cmp\tx\[0-9\]+, x\[0-9\]+" } } */
+  if (a > b)
+    return a + c;
+  else
+    return a + b + c;
+}
+
+s64
+cmp_di_test2 (s64 a, s64 b, s64 c)
+{
+  /* { dg-final { scan-assembler "cmp\tx\[0-9\]+, x\[0-9\]+, asr 3" } } */
+  if ((a >> 3) > b)
+    return a + c;
+  else
+    return a + b + c;
+}
+
+int
+cmp_di_test3 (int a, s64 b, s64 c)
+{
+  /* { dg-final { scan-assembler "cmp\tx\[0-9\]+, x\[0-9\]+, sxtw" } } */
+  if (a > b)
+    return a + c;
+  else
+    return a + b + c;
+}
+
+int
+cmp_di_test4 (int a, s64 b, s64 c)
+{
+  /* { dg-final { scan-assembler "cmp\tx\[0-9\]+, x\[0-9\]+, sxtw 3" } } */
+  if (((s64)a << 3) > b)
+    return a + c;
+  else
+    return a + b + c;
+}
+
+int main ()
+{
+  int x;
+  s64 y;
+
+  x = cmp_si_test1 (2, 12, 5);
+  if (x != 19)
+    abort ();
+
+  x = cmp_si_test1 (1, 2, 32);
+  if (x != 35)
+    abort ();
+
+  x = cmp_si_test2 (7, 5, 15);
+  if (x != 27)
+    abort ();
+
+  x = cmp_si_test2 (12, 1, 3);
+  if (x != 16)
+    abort ();
+
+  y = cmp_di_test1 (0x20202020ll,
+		    0x65161611ll,
+		    0x42434243ll);
+  if (y != 0xc7797874ll)
+    abort ();
+
+  y = cmp_di_test1 (0x1010101010101ll,
+		    0x123456789abcdll,
+		    0x5555555555555ll);
+  if (y != 0x7799bbde00223ll)
+    abort ();
+
+  y = cmp_di_test2 (0x31313131ll,
+		    0x35466561ll,
+		    0x42434243ll);
+  if (y != 0xa8bad8d5ll)
+    abort ();
+
+  y = cmp_di_test2 (0x101010101ll,
+		    0x123456789ll,
+		    0x555555555ll);
+  if (y != 0x7799bbddfll)
+    abort ();
+
+  x = cmp_di_test3 (6252,
+                    0x64234978ll,
+                    0x12345123ll);
+  if (x != 1985458951)
+    abort ();
+
+  x = cmp_di_test3 (7635,
+                    0x10101010ll,
+                    0x21212121ll);
+  if (x != 825315076)
+    abort ();
+
+  x = cmp_di_test4 (202,
+                    0x984210421ll,
+                    0x18181818181ll);
+  if (x != 94537324)
+    abort ();
+
+  x = cmp_di_test4 (167,
+                    0x987987987987ll,
+                    0x12312312ll);
+  if (x != -1714840256)
+    abort ();
+
+  return 0;
+}