| Message ID | 1365749635-7025-3-git-send-email-b18965@freescale.com |
|---|---|
| State | Changes Requested |
| Delegated to: | Stefano Babic |
| Headers | show |
Hi Alison, On Fri, Apr 12, 2013 at 3:53 AM, Alison Wang <b18965@freescale.com> wrote: > This patch adds Freescale vybrid vf600 tower board support. > > Signed-off-by: TsiChung Liew <tsicliew@gmail.com> > Signed-off-by: Jason Jin <Jason.jin@freescale.com> > Signed-off-by: Alison Wang <b18965@freescale.com> > --- > board/freescale/vybrid/Makefile | 40 +++ > board/freescale/vybrid/vybrid.c | 488 +++++++++++++++++++++++++++++++++ Vybrid is the SoC name and the board name is vf600, right? Then you should add: board/freescale/vf600 Also, please copy Stefano Babic in your future patches, as he is the U-boot imx maintainer. > board/freescale/vybrid/vybridimage.cfg | 44 +++ > boards.cfg | 2 + > include/configs/vybrid.h | 284 +++++++++++++++++++ > include/configs/vybrid_iram.h | 284 +++++++++++++++++++ > 6 files changed, 1142 insertions(+) > create mode 100644 board/freescale/vybrid/Makefile > create mode 100644 board/freescale/vybrid/vybrid.c > create mode 100644 board/freescale/vybrid/vybridimage.cfg > create mode 100644 include/configs/vybrid.h > create mode 100644 include/configs/vybrid_iram.h This patch should be the last of the series. You add the board support here, but ethernet, serial, esdhc support comes later in the patch series. Please add an entry to MAINTAINERS file. > +#ifdef CONFIG_FSL_ESDHC > +struct fsl_esdhc_cfg esdhc_cfg[2] = { > + {CONFIG_SYS_ESDHC1_BASE, 1}, > + {ESDHC2_BASE_ADDR, 1}, CONFIG_ESDHC2_BASE_ADDR ? > +int dram_init(void) > +{ > + setup_iomux_ddr(); > +#ifdef CONFIG_SYS_UBOOT_IN_GPURAM You introduced CONFIG_SYS_UBOOT_IN_GPURAM here and it would be nice to add an entry into README explaining what it means. > + gd->ram_size = 0x80000; > + ddr_ctrl_init(); > +#else > + gd->ram_size = ddr_ctrl_init(); > +#endif > + return 0; Can't you use the standard method? gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); > +#ifdef CONFIG_QUAD_SPI CONFIG_QUAD_SPI does not exist in U-boot. Can't you re-use an existing SPI config option? > +#ifdef CONFIG_FSL_ESDHC > +int board_mmc_getcd(struct mmc *mmc) > +{ > + int ret; > + > + __raw_writel(0x005031ef, IOMUXC_PAD_014); /* clk */ > + __raw_writel(0x005031ef, IOMUXC_PAD_015); /* cmd */ > + __raw_writel(0x005031ef, IOMUXC_PAD_016); /* dat0 */ > + __raw_writel(0x005031ef, IOMUXC_PAD_017); /* dat1 */ > + __raw_writel(0x005031ef, IOMUXC_PAD_018); /* dat2 */ > + __raw_writel(0x005031ef, IOMUXC_PAD_019); /* dat3 */ This function should basically return the card detect status, please setup the IOMUX in another place. > + ret = 1; > + return ret; In this board you assume that the SD card is always present, right? You could remove the 'ret' variable. > diff --git a/board/freescale/vybrid/vybridimage.cfg b/board/freescale/vybrid/vybridimage.cfg > new file mode 100644 > index 0000000..5da5659 > --- /dev/null > +++ b/board/freescale/vybrid/vybridimage.cfg > @@ -0,0 +1,44 @@ > +# > +# Copyright 2012-2013 Freescale Semiconductor, Inc. > +# > +# See file CREDITS for list of people who contributed to this > +# project. > +# > +# This program is free software; you can redistribute it and/or > +# modify it under the terms of the GNU General Public License as > +# published by the Free Software Foundation; either version 2 of > +# the License or (at your option) any later version. > +# > +# This program is distributed in the hope that it will be useful, > +# but WITHOUT ANY WARRANTY; without even the implied warranty of > +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > +# GNU General Public License for more details. > +# > +# You should have received a copy of the GNU General Public License > +# along with this program; if not write to the Free Software > +# Foundation Inc. 51 Franklin Street Fifth Floor Boston, > +# MA 02110-1301 USA > +# > +# Refer docs/README.imxmage for more details about how-to configure > +# and create imximage boot image > +# > +# The syntax is taken as close as possible with the kwbimage > + > +IMAGE_VERSION 2 > + > +# Boot Device : one of > +# spi, sd (the board has no nand neither onenand) > + > +BOOT_FROM sd > + > +# Device Configuration Data (DCD) > +# > +# Each entry must have the format: > +# Addr-type Address Value > +# > +# where: > +# Addr-type register length (1,2 or 4 bytes) > +# Address absolute address of the register > +# value value to be stored in the register > + > +# Setting IOMUXC This file is suited for imx. If you don't need this for Vybrid, please remove it. > diff --git a/boards.cfg b/boards.cfg > index 7725a15..2700a76 100644 > --- a/boards.cfg > +++ b/boards.cfg > @@ -244,6 +244,8 @@ am335x_evm_uart5 arm armv7 am335x ti > am335x_evm_usbspl arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,SPL_USBETH_SUPPORT > pcm051 arm armv7 pcm051 phytec am33xx pcm051 > highbank arm armv7 highbank - highbank > +vybrid arm armv7 vybrid freescale vybrid vybrid:VYBRID_CONFIG=board/freescale/vybrid/vybridimage.cfg > +vybrid_iram arm armv7 vybrid freescale vybrid vybrid_iram:VYBRID_CONFIG=board/freescale/vybrid/vybridimage.cfg Looks like you don't need vybridimage.cfg. > mx51_efikamx arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg > mx51_efikasb arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg > mx51evk arm armv7 mx51evk freescale mx5 mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg > diff --git a/include/configs/vybrid.h b/include/configs/vybrid.h > new file mode 100644 > index 0000000..d915bd0 > --- /dev/null > +++ b/include/configs/vybrid.h > @@ -0,0 +1,284 @@ > +/* > + * Copyright 2012-2013 Freescale Semiconductor, Inc. > + * > + * Configuration settings for the vybrid Board Since Vybrid is the SoC name, I would expect the > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > + > +#ifndef __CONFIG_H > +#define __CONFIG_H > + > + /* High Level Configuration Options */ > + > +#define CONFIG_VYBRID > + > +#define CONFIG_SYS_VYBRID_HCLK 24000000 > +#define CONFIG_SYS_VYBRID_CLK32 32768 > +#define CONFIG_DISPLAY_CPUINFO > +#define CONFIG_DISPLAY_BOARDINFO > +#define CONFIG_SYS_IPG > + > +#define CONFIG_SYS_ICACHE_OFF > +#define CONFIG_SYS_CACHELINE_SIZE 64 > + > +#include <asm/arch/vybrid-regs.h> Move the include to the start of the file. > + > +/* > + * Disabled for now due to build problems under Debian and a significant > + * increase in the final file size: 144260 vs. 109536 Bytes. > + */ Please remove this comment. It does not apply here. > + > +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ > +#undef CONFIG_SETUP_MEMORY_TAGS > +#undef CONFIG_INITRD_TAG > + > +#undef CONFIG_OF_LIBFDT > + > +#define CONFIG_MACH_TYPE MACH_TYPE_VYBRID_VF6XX > +/* Size of malloc() pool */ > +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) > + > +#define CONFIG_BOARD_LATE_INIT > + > +/* Hardware drivers */ > +#define CONFIG_VYBRID_UART > +#define CONFIG_VYBRID_UART_BASE UART0_BASE > +#define CONFIG_VYBRID_GPIO > + > +/* allow to overwrite serial and ethaddr */ > +#define CONFIG_ENV_OVERWRITE > +#define CONFIG_SYS_UART_PORT (1) > +#define CONFIG_BAUDRATE 115200 > +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} > + > +/* Command definition */ > +#include <config_cmd_default.h> > + > +#define CONFIG_CMD_BDI /* bdinfo */ > +#define CONFIG_CMD_BOOTD > +#define CONFIG_CMD_CONSOLE /* coninfo */ > +#define CONFIG_CMD_DHCP > +#define CONFIG_CMD_ELF > +#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */ > +#define CONFIG_CMD_MISC > +#define CONFIG_CMD_MII > +#define CONFIG_CMD_NET > +#undef CONFIG_CMD_NFS /* NFS support */ Do you need to undef it? Just do not include it, right? > +#define CONFIG_CMD_PING > +#undef CONFIG_CMD_NAND Same here. > +#undef CONFIG_CMD_DATE Same here. > +#undef CONFIG_CMD_IMI /* iminfo */ > +#undef CONFIG_CMD_IMLS > +#undef CONFIG_CMD_LOADB /* loadb */ > +#undef CONFIG_CMD_LOADS /* loads */ > + > +#define CONFIG_SYS_TEXT_BASE 0x3f000800 > + > +#define CONFIG_MMC > +#ifdef CONFIG_MMC > +#define CONFIG_SYS_ESDHC1_BASE ESDHC2_BASE_ADDR > +#define CONFIG_SYS_ESDHC2_BASE ESDHC2_BASE_ADDR > +#define CONFIG_FSL_ESDHC > +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 > +#define CONFIG_SYS_FSL_ESDHC_NUM 1 > + > +#define CONFIG_SYS_FSL_ERRATUM_ESDHC135 > +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 > +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 > + > +#define CONFIG_CMD_MMC > +#define CONFIG_GENERIC_MMC > +#define CONFIG_CMD_FAT > +#define CONFIG_DOS_PARTITION > +#endif > + > +/* > + * NAND FLASH > + */ > +#ifdef CONFIG_CMD_NAND > +#define CONFIG_MTD_NAND_FSL_NFC_SWECC 1 > +#define CONFIG_JFFS2_NAND > +#define CONFIG_NAND_FSL_NFC > +#define CONFIG_SYS_NAND_BASE 0x400E0000 > +#define CONFIG_SYS_MAX_NAND_DEVICE 1 > +#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE > +#define CONFIG_SYS_NAND_SELECT_DEVICE > +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ > +#endif > + > +#define CONFIG_QUAD_SPI > + > +/* Network configuration */ > +#define CONFIG_MCFFEC > +#ifdef CONFIG_MCFFEC > +# define CONFIG_MII 1 > +# define CONFIG_MII_INIT 1 > +# define CONFIG_SYS_DISCOVER_PHY > +# define CONFIG_SYS_RX_ETH_BUFFER 8 > +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN > + > +# define CONFIG_SYS_FEC0_PINMUX 0 > +# define CONFIG_SYS_FEC1_PINMUX 0 > +# define CONFIG_SYS_FEC0_IOBASE MACNET0_BASE_ADDR > +# define CONFIG_SYS_FEC1_IOBASE MACNET1_BASE_ADDR > +# define CONFIG_SYS_FEC0_MIIBASE MACNET0_BASE_ADDR > +# define CONFIG_SYS_FEC1_MIIBASE MACNET0_BASE_ADDR > +# define MCFFEC_TOUT_LOOP 50000 > +# undef CONFIG_HAS_ETH1 > + > +# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 > +# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61 > +# define CONFIG_ETHPRIME "FEC0" > +# define CONFIG_IPADDR 10.81.67.175 > +# define CONFIG_NETMASK 255.255.252.0 > +# define CONFIG_SERVERIP 10.81.64.153 > +# define CONFIG_GATEWAYIP 10.81.67.254 > +# define CONFIG_OVERWRITE_ETHADDR_ONCE No hardcoded IP addresses/MAC addresses, please. > + > +/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ > +# ifndef CONFIG_SYS_DISCOVER_PHY > +# define FECDUPLEX FULL > +# define FECSPEED _100BASET > +# else > +# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN > +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN > +# endif > +# endif /* CONFIG_SYS_DISCOVER_PHY */ > +#endif > + > +#define CONFIG_BOOTDELAY 3 > +#define CONFIG_ETHPRIME "FEC0" > +#define CONFIG_LOADADDR 0x80010000 /* loadaddr env var */ > +#define CONFIG_ARP_TIMEOUT 200UL Is this really needed? > diff --git a/include/configs/vybrid_iram.h b/include/configs/vybrid_iram.h > new file mode 100644 > index 0000000..f88050e > --- /dev/null > +++ b/include/configs/vybrid_iram.h Do we really need two configs? Can't we have just one?
On Sat, Apr 13, 2013 at 2:15 AM, Wang Huan-B18965 <B18965@freescale.com> wrote: > No hardcoded IP addresses/MAC addresses, please. > > [Alison] Agree. What is the general configuration way for these default settings? Just remove it from the config file. For IP addresses, the user should manually set serverip/ipaddr, etc in the U-boot prompt. For MAC addresses usually we read it from fuses, Regards, Fabio Estevam
On 12/04/2013 08:53, Alison Wang wrote: > This patch adds Freescale vybrid vf600 tower board support. > > Signed-off-by: TsiChung Liew <tsicliew@gmail.com> > Signed-off-by: Jason Jin <Jason.jin@freescale.com> > Signed-off-by: Alison Wang <b18965@freescale.com> > --- Hi Alison. > board/freescale/vybrid/Makefile | 40 +++ > board/freescale/vybrid/vybrid.c | 488 +++++++++++++++++++++++++++++++++ > board/freescale/vybrid/vybridimage.cfg | 44 +++ > boards.cfg | 2 + > include/configs/vybrid.h | 284 +++++++++++++++++++ > include/configs/vybrid_iram.h | 284 +++++++++++++++++++ > 6 files changed, 1142 insertions(+) > create mode 100644 board/freescale/vybrid/Makefile > create mode 100644 board/freescale/vybrid/vybrid.c > create mode 100644 board/freescale/vybrid/vybridimage.cfg > create mode 100644 include/configs/vybrid.h > create mode 100644 include/configs/vybrid_iram.h > > diff --git a/board/freescale/vybrid/Makefile b/board/freescale/vybrid/Makefile > new file mode 100644 > index 0000000..0749b21 > --- /dev/null > +++ b/board/freescale/vybrid/Makefile > @@ -0,0 +1,40 @@ > +# > +# Copyright 2012-2013 Freescale Semiconductor, Inc. > +# > +# This program is free software; you can redistribute it and/or > +# modify it under the terms of the GNU General Public License as > +# published by the Free Software Foundation; either version 2 of > +# the License, or (at your option) any later version. > +# > +# This program is distributed in the hope that it will be useful, > +# but WITHOUT ANY WARRANTY; without even the implied warranty of > +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > +# GNU General Public License for more details. > +# > +# You should have received a copy of the GNU General Public License > +# along with this program; if not, write to the Free Software > +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, > +# MA 02111-1307 USA > +# > + > +include $(TOPDIR)/config.mk > + > +LIB = $(obj)lib$(BOARD).o > + > +COBJS := $(BOARD).o > + > +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) > +OBJS := $(addprefix $(obj),$(COBJS)) > +SOBJS := $(addprefix $(obj),$(SOBJS)) > + > +$(LIB): $(obj).depend $(OBJS) $(SOBJS) > + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) > + > +######################################################################### > + > +# defines $(obj).depend target > +include $(SRCTREE)/rules.mk > + > +sinclude $(obj).depend > + > +######################################################################### > diff --git a/board/freescale/vybrid/vybrid.c b/board/freescale/vybrid/vybrid.c > new file mode 100644 > index 0000000..c2da1ff > --- /dev/null > +++ b/board/freescale/vybrid/vybrid.c > @@ -0,0 +1,488 @@ > +/* > + * Copyright 2012-2013 Freescale Semiconductor, Inc. > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > + > +#include <common.h> > +#include <asm/io.h> > +#include <asm/fec.h> > +#include <asm/arch/vybrid-regs.h> > +#include <asm/arch/vybrid-pins.h> > +#include <asm/arch/iomux.h> > +#include <asm/errno.h> > +#include <asm/arch/sys_proto.h> > +#include <i2c.h> > +#include <mmc.h> > +#include <fsl_esdhc.h> > +#include <usb/ehci-fsl.h> > + > +DECLARE_GLOBAL_DATA_PTR; > + > +#define DDR_IOMUX 0x00000180 > +#define DDR_IOMUX1 0x00010180 > + > +#define PHY_DQ_TIMING 0x00002613 > +#define PHY_DQS_TIMING 0x00002615 > +#define PHY_CTRL 0x01210080 > +#define PHY_MASTER_CTRL 0x0001012a > +#define PHY_SLAVE_CTRL 0x00012020 > + > +#ifdef CONFIG_FSL_ESDHC > +struct fsl_esdhc_cfg esdhc_cfg[2] = { > + {CONFIG_SYS_ESDHC1_BASE, 1}, > + {ESDHC2_BASE_ADDR, 1}, > +}; > +#endif > + > +void setup_iomux_ddr(void) > +{ > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A15); > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A14); > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A13); > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A12); > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A11); > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A10); > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A9); > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A8); > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A7); > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A6); > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A5); > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A4); > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A3); > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A2); > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A1); > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_BA2); > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_BA1); > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_BA0); > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_CAS); > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_CKE); > + __raw_writel(DDR_IOMUX1, IOMUXC_DDR_CLK); > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_CS); > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D15); > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D14); > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D13); > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D12); > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D11); > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D10); > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D9); > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D8); > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D7); > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D6); > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D5); > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D4); > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D3); > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D2); > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D1); > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D0); > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_DQM1); > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_DQM0); > + __raw_writel(DDR_IOMUX1, IOMUXC_DDR_DQS1); > + __raw_writel(DDR_IOMUX1, IOMUXC_DDR_DQS0); > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_RAS); > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_WE); > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_ODT1); > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_ODT0); > +} > + > +void ddr_phy_init(void) > +{ > + /* phy_dq_timing_reg freq set 0 */ > + __raw_writel(PHY_DQ_TIMING, DDR_PHY000); > + __raw_writel(PHY_DQ_TIMING, DDR_PHY016); > + __raw_writel(PHY_DQ_TIMING, DDR_PHY032); > + __raw_writel(PHY_DQ_TIMING, DDR_PHY048); > + > + /* phy_dqs_timing_reg freq set 0 */ > + __raw_writel(PHY_DQS_TIMING, DDR_PHY001); > + __raw_writel(PHY_DQS_TIMING, DDR_PHY017); > + __raw_writel(PHY_DQS_TIMING, DDR_PHY033); > + __raw_writel(PHY_DQS_TIMING, DDR_PHY049); > + > + /* phy_gate_lpbk_ctrl_reg freq set 0 */ > + __raw_writel(PHY_CTRL, DDR_PHY002); /* read delay bit21:19 */ > + __raw_writel(PHY_CTRL, DDR_PHY018); /* phase_detect_sel bit18:16 */ > + __raw_writel(PHY_CTRL, DDR_PHY034); /* bit lpbk_ctrl bit12 */ > + __raw_writel(PHY_CTRL, DDR_PHY050); > + > + /* phy_dll_master_ctrl_reg freq set 0 */ > + __raw_writel(PHY_MASTER_CTRL, DDR_PHY003); > + __raw_writel(PHY_MASTER_CTRL, DDR_PHY019); > + __raw_writel(PHY_MASTER_CTRL, DDR_PHY035); > + __raw_writel(PHY_MASTER_CTRL, DDR_PHY051); > + > + /* phy_dll_slave_ctrl_reg freq set 0 */ > + __raw_writel(PHY_SLAVE_CTRL, DDR_PHY004); > + __raw_writel(PHY_SLAVE_CTRL, DDR_PHY020); > + __raw_writel(PHY_SLAVE_CTRL, DDR_PHY036); > + __raw_writel(PHY_SLAVE_CTRL, DDR_PHY052); > + > + __raw_writel(0x00001105, DDR_PHY050); > +} > + > +unsigned long ddr_ctrl_init(void) > +{ > + int dram_size, rows, cols, banks, port; > + > + __raw_writel(0x00000600, DDR_CR000); /* LPDDR2 or DDR3 */ > + __raw_writel(0x00000020, DDR_CR002); /* TINIT */ > + __raw_writel(0x0000007c, DDR_CR010); /* reset during power on */ > + /* warm boot - 200ns */ > + __raw_writel(0x00013880, DDR_CR011); /* 500us - 10ns */ > + __raw_writel(0x0000050c, DDR_CR012); /* CASLAT_LIN, WRLAT */ > + __raw_writel(0x15040404, DDR_CR013); /* trc, trrd, tccd > + tbst_int_interval */ > + __raw_writel(0x1406040F, DDR_CR014); /* tfaw, tfp, twtr, tras_min */ > + __raw_writel(0x04040000, DDR_CR016); /* tmrd, trtp */ > + __raw_writel(0x006DB00C, DDR_CR017); /* tras_max, tmod */ > + __raw_writel(0x00000403, DDR_CR018); /* tckesr, tcke */ > + > + __raw_writel(0x01000000, DDR_CR020); /* ap, writrp */ > + __raw_writel(0x06060101, DDR_CR021); /* trcd_int, tras_lockout > + ccAP */ > + __raw_writel(0x000B0000, DDR_CR022); /* tdal */ > + __raw_writel(0x03000200, DDR_CR023); /* bstlen, tmrr, tdll */ > + __raw_writel(0x00000006, DDR_CR024); /* addr_mirror, reg_dimm > + trp_ab */ > + __raw_writel(0x00010000, DDR_CR025); /* tref_enable, auto_refresh > + arefresh */ > + __raw_writel(0x0C28002C, DDR_CR026); /* tref, trfc */ > + __raw_writel(0x00000005, DDR_CR028); /* tref_interval fixed at 5 */ > + __raw_writel(0x00000003, DDR_CR029); /* tpdex */ > + > + __raw_writel(0x0000000A, DDR_CR030); /* txpdll */ > + __raw_writel(0x00440200, DDR_CR031); /* txsnr, txsr */ > + __raw_writel(0x00010000, DDR_CR033); /* cke_dly, en_quick_srefresh > + * srefresh_exit_no_refresh, > + * pwr, srefresh_exit > + */ > + __raw_writel(0x00050500, DDR_CR034); /* cksrx, */ > + /* cksre, lowpwr_ref_en */ > + > + /* Frequency change */ > + __raw_writel(0x00000100, DDR_CR038); /* freq change... */ > + __raw_writel(0x04001002, DDR_CR039); > + > + __raw_writel(0x00000001, DDR_CR041); /* dfi_init_start */ > + __raw_writel(0x00000000, DDR_CR045); /* wrmd */ > + __raw_writel(0x00000000, DDR_CR046); /* rdmd */ > + __raw_writel(0x00000000, DDR_CR047); /* REF_PER_AUTO_TEMPCHK: > + * LPDDR2 set to 2, else 0 > + */ > + > + /* DRAM device Mode registers */ > + __raw_writel(0x00460420, DDR_CR048); /* mr0, ddr3 burst of 8 only > + * mr1, if freq < 125 > + * dll_dis = 1, rtt = 0 > + * if freq > 125, dll_dis = 0 > + * rtt = 3 > + */ > + __raw_writel(0x00000000, DDR_CR049); /* mr2 */ > + __raw_writel(0x00000000, DDR_CR051); /* mr3 & mrsingle_data_0 */ > + > + __raw_writel(0x00000000, DDR_CR057); /* ctrl_raw */ > + > + /* ZQ stuff */ > + __raw_writel(0x01000200, DDR_CR066); /* zqcl, zqinit */ > + __raw_writel(0x02000040, DDR_CR067); /* zqcs */ > + __raw_writel(0x00000200, DDR_CR069); /* zq_on_sref_exit, qz_req */ > + > + __raw_writel(0x00000040, DDR_CR070); /* ref_per_zq */ > + __raw_writel(0x00000000, DDR_CR071); /* zqreset, ddr3 set to 0 */ > + __raw_writel(0x01000000, DDR_CR072); /* zqcs_rotate, no_zq_init */ > + > + /* DRAM controller misc */ > + __raw_writel(0x0a010300, DDR_CR073); /* arebit, col_diff, row_diff > + bank_diff */ > + __raw_writel(0x0101ffff, DDR_CR074); /* bank_split, addr_cmp_en > + cmd/age cnt */ > + __raw_writel(0x01010101, DDR_CR075); /* rw same pg, rw same en > + pri en, plen */ > + __raw_writel(0x03030101, DDR_CR076); /* #q_entries_act_dis > + * (#cmdqueues > + * dis_rw_grp_w_bnk_conflict > + * w2r_split_en, cs_same_en */ > + __raw_writel(0x01000101, DDR_CR077); /* cs_map, inhibit_dram_cmd > + * dis_interleave, swen */ > + __raw_writel(0x0000000C, DDR_CR078); /* qfull, lpddr2_s4, reduc > + burst_on_fly */ > + __raw_writel(0x01000000, DDR_CR079); /* ctrlupd_req_per aref en > + * ctrlupd_req > + * ctrller busy > + * in_ord_accept */ > + /* disable interrupts */ > + __raw_writel(0x1FFFFFFF, DDR_CR082); > + > + /* ODT */ > + __raw_writel(0x01010000, DDR_CR087); /* odt: wr_map_cs0 > + * rd_map_cs0 > + * port_data_err_id */ > + __raw_writel(0x00040000, DDR_CR088); /* todtl_2cmd */ > + __raw_writel(0x00000002, DDR_CR089); /* add_odt stuff */ > + > + __raw_writel(0x00020000, DDR_CR091); > + __raw_writel(0x00000000, DDR_CR092); /* tdqsck _min, max */ > + > + __raw_writel(0x00002819, DDR_CR096); /* wlmrd, wldqsen */ > + > + /* AXI ports */ > + __raw_writel(0x00202000, DDR_CR105); > + __raw_writel(0x20200000, DDR_CR106); > + __raw_writel(0x00002020, DDR_CR110); > + __raw_writel(0x00202000, DDR_CR114); > + __raw_writel(0x20200000, DDR_CR115); > + > + __raw_writel(0x00000101, DDR_CR117); /* FIFO type (0-async, 1-2:1 > + * 2-1:2, 3- sync, w_pri > + * r_pri > + */ > + __raw_writel(0x01010000, DDR_CR118); /* w_pri, rpri, en */ > + __raw_writel(0x00000000, DDR_CR119); /* fifo_type */ > + > + __raw_writel(0x02020000, DDR_CR120); > + __raw_writel(0x00000202, DDR_CR121); > + __raw_writel(0x01010064, DDR_CR122); > + __raw_writel(0x00000101, DDR_CR123); > + __raw_writel(0x00000064, DDR_CR124); > + > + /* TDFI */ > + __raw_writel(0x00000000, DDR_CR125); > + __raw_writel(0x00000B00, DDR_CR126); /* PHY rdlat */ > + __raw_writel(0x00000000, DDR_CR127); /* dram ck dis */ > + > + __raw_writel(0x00000000, DDR_CR131); > + __raw_writel(0x00000506, DDR_CR132); /* wrlat, rdlat */ > + __raw_writel(0x02000000, DDR_CR137); > + __raw_writel(0x04070303, DDR_CR139); > + > + __raw_writel(0x00000000, DDR_CR136); > + > + __raw_writel(0x68200000, DDR_CR154); > + __raw_writel(0x00000202, DDR_CR155); /* pad_ibe, _sel */ > + __raw_writel(0x00000006, DDR_CR158); /* twr */ > + __raw_writel(0x00000006, DDR_CR159); /* todth */ > + > + ddr_phy_init(); > + > + __raw_writel(0x00000601, DDR_CR000); /* LPDDR2 or DDR3, start */ > + > + udelay(200); > + > + rows = (__raw_readl(DDR_CR001) & 0x1F) - > + ((__raw_readl(DDR_CR073) >> 8) & 3); > + cols = ((__raw_readl(DDR_CR001) >> 8) & 0xF) - > + ((__raw_readl(DDR_CR073) >> 16) & 7); > + banks = 1 << (3 - (__raw_readl(DDR_CR073) & 3)); > + port = ((__raw_readl(DDR_CR078) >> 8) & 1) ? 1 : 2; > + > + dram_size = (1 << (rows + cols)) * banks * port; > + > + return dram_size; > +} > + > +int dram_init(void) > +{ > + setup_iomux_ddr(); > +#ifdef CONFIG_SYS_UBOOT_IN_GPURAM > + gd->ram_size = 0x80000; > + ddr_ctrl_init(); > +#else > + gd->ram_size = ddr_ctrl_init(); > +#endif > + return 0; > +} > + > +void setup_iomux_uart(void) > +{ > + __raw_writel(0x002011a2, IOMUXC_PAD_026); > + __raw_writel(0x002011a1, IOMUXC_PAD_027); > + __raw_writel(0x002011a2, IOMUXC_PAD_028); > + __raw_writel(0x002011a1, IOMUXC_PAD_029); > + __raw_writel(0x001011a2, IOMUXC_PAD_032); > + __raw_writel(0x001011a1, IOMUXC_PAD_033); > +} > + > +#ifdef CONFIG_CMD_NET > +int fecpin_setclear(struct eth_device *dev, int setclear) > +{ > + struct fec_info_s *info = (struct fec_info_s *)dev->priv; > + > + __raw_writel(0x00203191, IOMUXC_PAD_000); /* RMII_CLK */ > + > + if (setclear) { > + if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { > + __raw_writel(0x00103192, IOMUXC_PAD_045); /*MDC*/ > + __raw_writel(0x00103193, IOMUXC_PAD_046); /*MDIO*/ > + __raw_writel(0x00103191, IOMUXC_PAD_047); /*RxDV*/ > + __raw_writel(0x00103191, IOMUXC_PAD_048); /*RxD1*/ > + __raw_writel(0x00103191, IOMUXC_PAD_049); /*RxD0*/ > + __raw_writel(0x00103191, IOMUXC_PAD_050); /*RxER*/ > + __raw_writel(0x00103192, IOMUXC_PAD_051); /*TxD1*/ > + __raw_writel(0x00103192, IOMUXC_PAD_052); /*TxD0*/ > + __raw_writel(0x00103192, IOMUXC_PAD_053); /*TxEn*/ > + } > + if (info->iobase == CONFIG_SYS_FEC1_IOBASE) { > + __raw_writel(0x00103192, IOMUXC_PAD_054); /*MDC*/ > + __raw_writel(0x00103193, IOMUXC_PAD_055); /*MDIO*/ > + __raw_writel(0x00103191, IOMUXC_PAD_056); /*RxDV*/ > + __raw_writel(0x00103191, IOMUXC_PAD_057); /*RxD1*/ > + __raw_writel(0x00103191, IOMUXC_PAD_058); /*RxD0*/ > + __raw_writel(0x00103191, IOMUXC_PAD_059); /*RxER*/ > + __raw_writel(0x00103192, IOMUXC_PAD_060); /*TxD1*/ > + __raw_writel(0x00103192, IOMUXC_PAD_061); /*TxD0*/ > + __raw_writel(0x00103192, IOMUXC_PAD_062); /*TxEn*/ > + } > + } else { > + if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { > + __raw_writel(0x00003192, IOMUXC_PAD_045); /*MDC*/ > + __raw_writel(0x00003193, IOMUXC_PAD_046); /*MDIO*/ > + __raw_writel(0x00003191, IOMUXC_PAD_047); /*RxDV*/ > + __raw_writel(0x00003191, IOMUXC_PAD_048); /*RxD1*/ > + __raw_writel(0x00003191, IOMUXC_PAD_049); /*RxD0*/ > + __raw_writel(0x00003191, IOMUXC_PAD_050); /*RxER*/ > + __raw_writel(0x00003192, IOMUXC_PAD_051); /*TxD1*/ > + __raw_writel(0x00003192, IOMUXC_PAD_052); /*TxD0*/ > + __raw_writel(0x00003192, IOMUXC_PAD_053); /*TxEn*/ > + } > + if (info->iobase == CONFIG_SYS_FEC1_IOBASE) { > + __raw_writel(0x00003192, IOMUXC_PAD_054); /*MDC*/ > + __raw_writel(0x00003193, IOMUXC_PAD_055); /*MDIO*/ > + __raw_writel(0x00003191, IOMUXC_PAD_056); /*RxDV*/ > + __raw_writel(0x00003191, IOMUXC_PAD_057); /*RxD1*/ > + __raw_writel(0x00003191, IOMUXC_PAD_058); /*RxD0*/ > + __raw_writel(0x00003191, IOMUXC_PAD_059); /*RxER*/ > + __raw_writel(0x00003192, IOMUXC_PAD_060); /*TxD1*/ > + __raw_writel(0x00003192, IOMUXC_PAD_061); /*TxD0*/ > + __raw_writel(0x00003192, IOMUXC_PAD_062); /*TxEn*/ > + } > + } > + > + return 0; > +} > +#endif > + > +#ifdef CONFIG_QUAD_SPI > +void setup_iomux_quadspi(void) > +{ > + __raw_writel(0x001030C3, IOMUXC_PAD_079); /* SCK */ > + __raw_writel(0x001030FF, IOMUXC_PAD_080); /* CS0 */ > + __raw_writel(0x001030C3, IOMUXC_PAD_081); /* D3 */ > + __raw_writel(0x001030C3, IOMUXC_PAD_082); /* D2 */ > + __raw_writel(0x001030C3, IOMUXC_PAD_083); /* D1 */ > + __raw_writel(0x001030C3, IOMUXC_PAD_084); /* D0 */ > + > + __raw_writel(0x001030C3, IOMUXC_PAD_086); /* SCK */ > + __raw_writel(0x001030FF, IOMUXC_PAD_087); /* CS0 */ > + __raw_writel(0x001030C3, IOMUXC_PAD_088); /* D3 */ > + __raw_writel(0x001030C3, IOMUXC_PAD_089); /* D2 */ > + __raw_writel(0x001030C3, IOMUXC_PAD_090); /* D1 */ > + __raw_writel(0x001030C3, IOMUXC_PAD_091); /* D0 */ > +} > +#endif > + > +#ifdef CONFIG_FSL_ESDHC > +int board_mmc_getcd(struct mmc *mmc) > +{ > + int ret; > + > + __raw_writel(0x005031ef, IOMUXC_PAD_014); /* clk */ > + __raw_writel(0x005031ef, IOMUXC_PAD_015); /* cmd */ > + __raw_writel(0x005031ef, IOMUXC_PAD_016); /* dat0 */ > + __raw_writel(0x005031ef, IOMUXC_PAD_017); /* dat1 */ > + __raw_writel(0x005031ef, IOMUXC_PAD_018); /* dat2 */ > + __raw_writel(0x005031ef, IOMUXC_PAD_019); /* dat3 */ > + > + ret = 1; > + return ret; > +} > + > +int board_mmc_init(bd_t *bis) > +{ > + u32 index = 0; > + s32 status = 0; > + > + esdhc_cfg[0].sdhc_clk = 132000000; > + esdhc_cfg[1].sdhc_clk = 132000000; > + status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]); > + return status; > +} > +#endif > + > +#ifdef CONFIG_NAND_FSL_NFC > +void setup_iomux_nfc(void) > +{ > + __raw_writel(0x002038df, IOMUXC_PAD_063); > + __raw_writel(0x002038df, IOMUXC_PAD_064); > + __raw_writel(0x002038df, IOMUXC_PAD_065); > + __raw_writel(0x002038df, IOMUXC_PAD_066); > + __raw_writel(0x002038df, IOMUXC_PAD_067); > + __raw_writel(0x002038df, IOMUXC_PAD_068); > + __raw_writel(0x002038df, IOMUXC_PAD_069); > + __raw_writel(0x002038df, IOMUXC_PAD_070); > + __raw_writel(0x002038df, IOMUXC_PAD_071); > + __raw_writel(0x002038df, IOMUXC_PAD_072); > + __raw_writel(0x002038df, IOMUXC_PAD_073); > + __raw_writel(0x002038df, IOMUXC_PAD_074); > + __raw_writel(0x002038df, IOMUXC_PAD_075); > + __raw_writel(0x002038df, IOMUXC_PAD_076); > + __raw_writel(0x002038df, IOMUXC_PAD_077); > + __raw_writel(0x002038df, IOMUXC_PAD_078); > + > + __raw_writel(0x005038d2, IOMUXC_PAD_094); > + __raw_writel(0x005038d2, IOMUXC_PAD_095); > + __raw_writel(0x006038d2, IOMUXC_PAD_097); > + __raw_writel(0x005038dd, IOMUXC_PAD_099); > + __raw_writel(0x006038d2, IOMUXC_PAD_100); > + __raw_writel(0x006038d2, IOMUXC_PAD_101); > +} > +#endif > + > +int board_early_init_f(void) > +{ > + setup_iomux_uart(); > +#ifdef CONFIG_NAND_FSL_NFC > + setup_iomux_nfc(); > +#endif > + return 0; > +} > + > +int board_init(void) > +{ > + /* address of boot parameters */ > + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; > + > + return 0; > +} > + > +#ifdef CONFIG_BOARD_LATE_INIT > +int board_late_init(void) > +{ > +#ifdef CONFIG_MXC_SPI > + setup_iomux_spi(); > +#endif > + return 0; > +} > +#endif > + > +int checkboard(void) > +{ > + puts("Board: Vybrid\n"); > + > + return 0; > +} > diff --git a/board/freescale/vybrid/vybridimage.cfg b/board/freescale/vybrid/vybridimage.cfg > new file mode 100644 > index 0000000..5da5659 > --- /dev/null > +++ b/board/freescale/vybrid/vybridimage.cfg > @@ -0,0 +1,44 @@ > +# > +# Copyright 2012-2013 Freescale Semiconductor, Inc. > +# > +# See file CREDITS for list of people who contributed to this > +# project. > +# > +# This program is free software; you can redistribute it and/or > +# modify it under the terms of the GNU General Public License as > +# published by the Free Software Foundation; either version 2 of > +# the License or (at your option) any later version. > +# > +# This program is distributed in the hope that it will be useful, > +# but WITHOUT ANY WARRANTY; without even the implied warranty of > +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > +# GNU General Public License for more details. > +# > +# You should have received a copy of the GNU General Public License > +# along with this program; if not write to the Free Software > +# Foundation Inc. 51 Franklin Street Fifth Floor Boston, > +# MA 02110-1301 USA > +# > +# Refer docs/README.imxmage for more details about how-to configure > +# and create imximage boot image > +# > +# The syntax is taken as close as possible with the kwbimage > + > +IMAGE_VERSION 2 > + > +# Boot Device : one of > +# spi, sd (the board has no nand neither onenand) > + > +BOOT_FROM sd > + > +# Device Configuration Data (DCD) > +# > +# Each entry must have the format: > +# Addr-type Address Value > +# > +# where: > +# Addr-type register length (1,2 or 4 bytes) > +# Address absolute address of the register > +# value value to be stored in the register > + > +# Setting IOMUXC > diff --git a/boards.cfg b/boards.cfg > index 7725a15..2700a76 100644 > --- a/boards.cfg > +++ b/boards.cfg > @@ -244,6 +244,8 @@ am335x_evm_uart5 arm armv7 am335x ti > am335x_evm_usbspl arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,SPL_USBETH_SUPPORT > pcm051 arm armv7 pcm051 phytec am33xx pcm051 > highbank arm armv7 highbank - highbank > +vybrid arm armv7 vybrid freescale vybrid vybrid:VYBRID_CONFIG=board/freescale/vybrid/vybridimage.cfg > +vybrid_iram arm armv7 vybrid freescale vybrid vybrid_iram:VYBRID_CONFIG=board/freescale/vybrid/vybridimage.cfg > mx51_efikamx arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg > mx51_efikasb arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg > mx51evk arm armv7 mx51evk freescale mx5 mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg > diff --git a/include/configs/vybrid.h b/include/configs/vybrid.h > new file mode 100644 > index 0000000..d915bd0 > --- /dev/null > +++ b/include/configs/vybrid.h > @@ -0,0 +1,284 @@ > +/* > + * Copyright 2012-2013 Freescale Semiconductor, Inc. > + * > + * Configuration settings for the vybrid Board > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > + > +#ifndef __CONFIG_H > +#define __CONFIG_H > + > + /* High Level Configuration Options */ > + > +#define CONFIG_VYBRID > + > +#define CONFIG_SYS_VYBRID_HCLK 24000000 > +#define CONFIG_SYS_VYBRID_CLK32 32768 > +#define CONFIG_DISPLAY_CPUINFO > +#define CONFIG_DISPLAY_BOARDINFO > +#define CONFIG_SYS_IPG > + > +#define CONFIG_SYS_ICACHE_OFF > +#define CONFIG_SYS_CACHELINE_SIZE 64 > + > +#include <asm/arch/vybrid-regs.h> > + > +/* > + * Disabled for now due to build problems under Debian and a significant > + * increase in the final file size: 144260 vs. 109536 Bytes. > + */ > + > +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ > +#undef CONFIG_SETUP_MEMORY_TAGS > +#undef CONFIG_INITRD_TAG > + > +#undef CONFIG_OF_LIBFDT > + > +#define CONFIG_MACH_TYPE MACH_TYPE_VYBRID_VF6XX > +/* Size of malloc() pool */ > +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) > + > +#define CONFIG_BOARD_LATE_INIT > + > +/* Hardware drivers */ > +#define CONFIG_VYBRID_UART > +#define CONFIG_VYBRID_UART_BASE UART0_BASE > +#define CONFIG_VYBRID_GPIO > + > +/* allow to overwrite serial and ethaddr */ > +#define CONFIG_ENV_OVERWRITE > +#define CONFIG_SYS_UART_PORT (1) > +#define CONFIG_BAUDRATE 115200 > +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} > + > +/* Command definition */ > +#include <config_cmd_default.h> > + > +#define CONFIG_CMD_BDI /* bdinfo */ > +#define CONFIG_CMD_BOOTD > +#define CONFIG_CMD_CONSOLE /* coninfo */ > +#define CONFIG_CMD_DHCP > +#define CONFIG_CMD_ELF > +#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */ > +#define CONFIG_CMD_MISC > +#define CONFIG_CMD_MII > +#define CONFIG_CMD_NET > +#undef CONFIG_CMD_NFS /* NFS support */ > +#define CONFIG_CMD_PING > +#undef CONFIG_CMD_NAND > +#undef CONFIG_CMD_DATE > +#undef CONFIG_CMD_IMI /* iminfo */ > +#undef CONFIG_CMD_IMLS > +#undef CONFIG_CMD_LOADB /* loadb */ > +#undef CONFIG_CMD_LOADS /* loads */ > + > +#define CONFIG_SYS_TEXT_BASE 0x3f000800 > + > +#define CONFIG_MMC > +#ifdef CONFIG_MMC > +#define CONFIG_SYS_ESDHC1_BASE ESDHC2_BASE_ADDR > +#define CONFIG_SYS_ESDHC2_BASE ESDHC2_BASE_ADDR > +#define CONFIG_FSL_ESDHC > +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 > +#define CONFIG_SYS_FSL_ESDHC_NUM 1 > + > +#define CONFIG_SYS_FSL_ERRATUM_ESDHC135 > +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 > +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 > + > +#define CONFIG_CMD_MMC > +#define CONFIG_GENERIC_MMC > +#define CONFIG_CMD_FAT > +#define CONFIG_DOS_PARTITION > +#endif > + > +/* > + * NAND FLASH > + */ > +#ifdef CONFIG_CMD_NAND > +#define CONFIG_MTD_NAND_FSL_NFC_SWECC 1 > +#define CONFIG_JFFS2_NAND > +#define CONFIG_NAND_FSL_NFC > +#define CONFIG_SYS_NAND_BASE 0x400E0000 > +#define CONFIG_SYS_MAX_NAND_DEVICE 1 > +#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE > +#define CONFIG_SYS_NAND_SELECT_DEVICE > +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ > +#endif > + > +#define CONFIG_QUAD_SPI > + > +/* Network configuration */ > +#define CONFIG_MCFFEC > +#ifdef CONFIG_MCFFEC > +# define CONFIG_MII 1 > +# define CONFIG_MII_INIT 1 > +# define CONFIG_SYS_DISCOVER_PHY > +# define CONFIG_SYS_RX_ETH_BUFFER 8 > +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN > + > +# define CONFIG_SYS_FEC0_PINMUX 0 > +# define CONFIG_SYS_FEC1_PINMUX 0 > +# define CONFIG_SYS_FEC0_IOBASE MACNET0_BASE_ADDR > +# define CONFIG_SYS_FEC1_IOBASE MACNET1_BASE_ADDR > +# define CONFIG_SYS_FEC0_MIIBASE MACNET0_BASE_ADDR > +# define CONFIG_SYS_FEC1_MIIBASE MACNET0_BASE_ADDR > +# define MCFFEC_TOUT_LOOP 50000 > +# undef CONFIG_HAS_ETH1 > + > +# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 > +# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61 > +# define CONFIG_ETHPRIME "FEC0" > +# define CONFIG_IPADDR 10.81.67.175 > +# define CONFIG_NETMASK 255.255.252.0 > +# define CONFIG_SERVERIP 10.81.64.153 > +# define CONFIG_GATEWAYIP 10.81.67.254 > +# define CONFIG_OVERWRITE_ETHADDR_ONCE > + > +/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ > +# ifndef CONFIG_SYS_DISCOVER_PHY > +# define FECDUPLEX FULL > +# define FECSPEED _100BASET > +# else > +# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN > +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN > +# endif > +# endif /* CONFIG_SYS_DISCOVER_PHY */ > +#endif > + > +#define CONFIG_BOOTDELAY 3 > +#define CONFIG_ETHPRIME "FEC0" > +#define CONFIG_LOADADDR 0x80010000 /* loadaddr env var */ > +#define CONFIG_ARP_TIMEOUT 200UL > + > +/* Miscellaneous configurable options */ > +#define CONFIG_SYS_LONGHELP /* undef to save memory */ > +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ > +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " > +#define CONFIG_SYS_PROMPT "Vybrid U-Boot > " > +#undef CONFIG_AUTO_COMPLETE > +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ > +/* Print Buffer Size */ > +#define CONFIG_SYS_PBSIZE \ > + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) > +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ > +/* Boot Argument Buffer Size */ > +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE > + > +#define CONFIG_SYS_MEMTEST_START 0x80010000 > +#define CONFIG_SYS_MEMTEST_END 0x87C00000 > + > +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR > + > +#define CONFIG_SYS_HZ 1000 > +#undef CONFIG_CMDLINE_EDITING > + > +#define CONFIG_PRAM 2048 > + > +/* > + * Stack sizes > + * The stack sizes are set up in start.S using the settings below > + */ > +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ > + > +/* Physical Memory Map */ > +#define CONFIG_NR_DRAM_BANKS 1 > +#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) > + > +#define CONFIG_SYS_SDRAM_BASE (0x80000000) > +#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) > +#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) > + > +#define CONFIG_BOARD_EARLY_INIT_F > + > +#define CONFIG_SYS_INIT_SP_OFFSET \ > + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) > +#define CONFIG_SYS_INIT_SP_ADDR \ > + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) > + > +/* timer */ > +#define FTM_BASE_ADDR FTM0_BASE_ADDR > +#define CONFIG_TMR_USEPIT > + > +/* clock/PLL configuration */ > +/* uart0-2 */ > +#define CONFIG_SYS_CLKCTL_CCGR0 0x000FC000 > +/* crc, pit, ftm0/1, a5/m4 wdog */ > +#define CONFIG_SYS_CLKCTL_CCGR1 0xF00FC0C0 > +/* lptmr, qspi0, iomuxc, gpio */ > +#define CONFIG_SYS_CLKCTL_CCGR2 0x0FFF0303 > +/* anadig, scscm*/ > +#define CONFIG_SYS_CLKCTL_CCGR3 0x00000033 > +/* acrc, i2c0/1, wkup, ccm, gpc, src */ > +#define CONFIG_SYS_CLKCTL_CCGR4 0x33f0f003 > +#define CONFIG_SYS_CLKCTL_CCGR5 0xFFFFFFFF > +/* ocotp, snvs, wdog_snvs, ddrmc */ > +#define CONFIG_SYS_CLKCTL_CCGR6 0x3003cc00 > +/* usb1, sdhc0/1 */ > +#define CONFIG_SYS_CLKCTL_CCGR7 0x0000033c > +/* qspi1 */ > +#define CONFIG_SYS_CLKCTL_CCGR8 0x00000300 > +/* enet0/1 */ > +#define CONFIG_SYS_CLKCTL_CCGR9 0x0000000f > +/* nfc */ > +#define CONFIG_SYS_CLKCTL_CCGR10 0x00000003 > +/* caam */ > +#define CONFIG_SYS_CLKCTL_CCGR11 0x00000003 > + > +#define CONFIG_SYS_CLKCTRL_CCR 0x00010005 > +#define CONFIG_SYS_CLKCTRL_CCSR 0x0003FF64 > +#define CONFIG_SYS_CLKCTRL_CACRR 0x00000810 > +#define CONFIG_SYS_CLKCTRL_CSCMR1 0x03CA0000 > +#define CONFIG_SYS_CLKCTRL_CSCDR1 0x01000000 > +#define CONFIG_SYS_CLKCTRL_CSCDR2 0x30114240 > +#define CONFIG_SYS_CLKCTRL_CSCDR3 0x00003F1F > +#define CONFIG_SYS_CLKCTRL_CSCMR2 0x00000000 > +#define CONFIG_SYS_CLKCTRL_CSCDR4 0x00000000 > +#define CONFIG_SYS_CLKCTRL_CLPCR 0x00000078 > + > +#define CONFIG_SYS_ANADIG_USB1_CTRL 0x00012000 > +#define CONFIG_SYS_ANADIG_USB2_CTRL 0x00012000 > +#define CONFIG_SYS_ANADIG_528_CTRL 0x00002001 > +#define CONFIG_SYS_ANADIG_528_SS 0x00000000 > +#define CONFIG_SYS_ANADIG_528_NUM 0x00000000 > +#define CONFIG_SYS_ANADIG_528_DENOM 0x00000012 > +#define CONFIG_SYS_ANADIG_VID_CTRL 0x00011028 > +#define CONFIG_SYS_ANADIG_VID_NUM 0x00000000 > +#define CONFIG_SYS_ANADIG_VID_DENOM 0x00000012 > +#define CONFIG_SYS_ANADIG_ENET_CTRL 0x00011001 > +#define CONFIG_SYS_ANADIG_PFD_USB1 0x1B1D1A1C > +#define CONFIG_SYS_ANADIG_PFD_528 0x171C1813 > +#define CONFIG_SYS_ANADIG_USB1_MISC 0x00000002 > +#define CONFIG_SYS_ANADIG_USB2_VBUS 0x00100004 > +#define CONFIG_SYS_ANADIG_USB2_CHRG 0x00000000 > +#define CONFIG_SYS_ANADIG_USB2_MISC 0x00000002 > +#define CONFIG_SYS_ANADIG_SYS_CTRL 0x00002001 > +#define CONFIG_SYS_ANADIG_SYS_SS 0x00000000 > +#define CONFIG_SYS_ANADIG_SYS_NUM 0x00000000 > +#define CONFIG_SYS_ANADIG_SYS_DENOM 0x00000012 > +#define CONFIG_SYS_ANADIG_SYS_PFD_528 0x00000000 > +#define CONFIG_SYS_ANADIG_SYS_PLL_LOCK 0x00000000 > + > +/* FLASH and environment organization */ > +#define CONFIG_SYS_NO_FLASH > + > +#define CONFIG_ENV_OFFSET (12 * 64 * 1024) > +#define CONFIG_ENV_SIZE (8 * 1024) > +#define CONFIG_ENV_IS_IN_MMC > +#define CONFIG_SYS_MMC_ENV_DEV 0 > + > +#endif > diff --git a/include/configs/vybrid_iram.h b/include/configs/vybrid_iram.h > new file mode 100644 > index 0000000..f88050e > --- /dev/null > +++ b/include/configs/vybrid_iram.h > @@ -0,0 +1,284 @@ > +/* > + * Copyright 2013 Freescale Semiconductor, Inc. > + * > + * Configuration settings for the vybrid Board > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > + As the name suggest, I am expecting that <soc>_iram.h contains the layout of the internal RAM, IRAM on Freescale's SOC. So the name is inconsistent with a board name. > +#ifndef __CONFIG_H > +#define __CONFIG_H > + > +/* High Level Configuration Options */ > + > +#define CONFIG_VYBRID > + > +#define CONFIG_SYS_VYBRID_HCLK 24000000 > +#define CONFIG_SYS_VYBRID_CLK32 32768 As I have already said, each CONFIG_SYS must be documented. Anyway, we get rid of these two defines in MX2x / MX3 /.. Do we really need them ? > +#define CONFIG_SYS_UBOOT_IN_GPURAM ??? > +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ > +#undef CONFIG_SETUP_MEMORY_TAGS > +#undef CONFIG_INITRD_TAG > + > +#undef CONFIG_OF_LIBFDT > + > +#define CONFIG_MACH_TYPE MACH_TYPE_VYBRID_VF6XX Set MACH_TYPE_VYBRID_VF6XX in this file > +/* Command definition */ > +#include <config_cmd_default.h> > + > +#define CONFIG_CMD_BDI /* bdinfo */ > +#define CONFIG_CMD_BOOTD > +#define CONFIG_CMD_CONSOLE /* coninfo */ > +#define CONFIG_CMD_DHCP > +#define CONFIG_CMD_ELF > +#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */ > +#define CONFIG_CMD_MISC > +#define CONFIG_CMD_MII > +#define CONFIG_CMD_NET > +#undef CONFIG_CMD_NFS /* NFS support */ > +#define CONFIG_CMD_PING > +#undef CONFIG_CMD_DATE > +#undef CONFIG_CMD_IMI /* iminfo */ > +#undef CONFIG_CMD_IMLS > +#undef CONFIG_CMD_LOADB /* loadb */ > +#undef CONFIG_CMD_LOADS /* loads */ > + > +#define CONFIG_SYS_TEXT_BASE 0x3f000800 > + > +#define CONFIG_MMC > +#ifdef CONFIG_MMC > +#define CONFIG_SYS_ESDHC1_BASE ESDHC2_BASE_ADDR > +#define CONFIG_SYS_ESDHC2_BASE ESDHC2_BASE_ADDR > +#define CONFIG_FSL_ESDHC > +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 > +#define CONFIG_SYS_FSL_ESDHC_NUM 1 > + > +#define CONFIG_SYS_FSL_ERRATUM_ESDHC135 > +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 > +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 Maybe correct, but they are up now defined only in PowerPC boards. Do you confirm that they are needed ? > +/* > + * NAND FLASH > + */ > +#ifdef CONFIG_CMD_NAND > +#define CONFIG_JFFS2_NAND > +#define CONFIG_NAND_FSL_NFC > +#define CONFIG_SYS_NAND_BASE 0x400E0000 > +#define CONFIG_SYS_MAX_NAND_DEVICE 1 > +#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE > +#define CONFIG_SYS_NAND_SELECT_DEVICE > +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ > +#endif Does the board have NAND ? I do not see the nand driver. > + > +/* Network configuration */ > +#define CONFIG_MCFFEC > +#ifdef CONFIG_MCFFEC > +# define CONFIG_MII 1 > +# define CONFIG_MII_INIT 1 > +# define CONFIG_SYS_DISCOVER_PHY > +# define CONFIG_SYS_RX_ETH_BUFFER 8 > +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN > + > +# define CONFIG_SYS_FEC0_PINMUX 0 > +# define CONFIG_SYS_FEC1_PINMUX 0 > +# define CONFIG_SYS_FEC0_IOBASE MACNET0_BASE_ADDR > +# define CONFIG_SYS_FEC1_IOBASE MACNET1_BASE_ADDR > +# define CONFIG_SYS_FEC0_MIIBASE MACNET0_BASE_ADDR > +# define CONFIG_SYS_FEC1_MIIBASE MACNET0_BASE_ADDR > +# define MCFFEC_TOUT_LOOP 50000 > +# undef CONFIG_HAS_ETH1 > + > +# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 > +# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61 Do not hardcode network addresses in u-boot > +/* timer */ > +#define FTM_BASE_ADDR FTM0_BASE_ADDR > +#define CONFIG_TMR_USEPIT > + > +/* clock/PLL configuration */ > +/* uart0-2 */ > +#define CONFIG_SYS_CLKCTL_CCGR0 0x000FC000 > +/* crc, pit, ftm0/1, a5/m4 wdog */ > +#define CONFIG_SYS_CLKCTL_CCGR1 0xF00FC0C0 > +/* lptmr, qspi0, iomuxc, gpio */ > +#define CONFIG_SYS_CLKCTL_CCGR2 0x0FFF0303 > +/* anadig, scscm*/ > +#define CONFIG_SYS_CLKCTL_CCGR3 0x00000033 > +/* acrc, i2c0/1, wkup, ccm, gpc, src */ > +#define CONFIG_SYS_CLKCTL_CCGR4 0x33f0f003 > +#define CONFIG_SYS_CLKCTL_CCGR5 0xFFFFFFFF > +/* ocotp, snvs, wdog_snvs, ddrmc */ > +#define CONFIG_SYS_CLKCTL_CCGR6 0x3003cc00 > +/* usb1, sdhc0/1 */ > +#define CONFIG_SYS_CLKCTL_CCGR7 0x0000033c > +/* qspi1 */ > +#define CONFIG_SYS_CLKCTL_CCGR8 0x00000300 > +/* enet0/1 */ > +#define CONFIG_SYS_CLKCTL_CCGR9 0x0000000f > +/* nfc */ > +#define CONFIG_SYS_CLKCTL_CCGR10 0x00000003 > +/* caam */ > +#define CONFIG_SYS_CLKCTL_CCGR11 0x00000003 > + > +#define CONFIG_SYS_CLKCTRL_CCR 0x00010005 > +#define CONFIG_SYS_CLKCTRL_CCSR 0x0003FF64 > +#define CONFIG_SYS_CLKCTRL_CACRR 0x00000810 > +#define CONFIG_SYS_CLKCTRL_CSCMR1 0x03CA0000 > +#define CONFIG_SYS_CLKCTRL_CSCDR1 0x01000000 > +#define CONFIG_SYS_CLKCTRL_CSCDR2 0x30114240 > +#define CONFIG_SYS_CLKCTRL_CSCDR3 0x00003F1F > +#define CONFIG_SYS_CLKCTRL_CSCMR2 0x00000000 > +#define CONFIG_SYS_CLKCTRL_CSCDR4 0x00000000 > +#define CONFIG_SYS_CLKCTRL_CLPCR 0x00000078 > + > +#define CONFIG_SYS_ANADIG_USB1_CTRL 0x00012000 > +#define CONFIG_SYS_ANADIG_USB2_CTRL 0x00012000 > +#define CONFIG_SYS_ANADIG_528_CTRL 0x00002001 > +#define CONFIG_SYS_ANADIG_528_SS 0x00000000 > +#define CONFIG_SYS_ANADIG_528_NUM 0x00000000 > +#define CONFIG_SYS_ANADIG_528_DENOM 0x00000012 > +#define CONFIG_SYS_ANADIG_VID_CTRL 0x00011028 > +#define CONFIG_SYS_ANADIG_VID_NUM 0x00000000 > +#define CONFIG_SYS_ANADIG_VID_DENOM 0x00000012 > +#define CONFIG_SYS_ANADIG_ENET_CTRL 0x00011001 > +#define CONFIG_SYS_ANADIG_PFD_USB1 0x1B1D1A1C > +#define CONFIG_SYS_ANADIG_PFD_528 0x171C1813 > +#define CONFIG_SYS_ANADIG_USB1_MISC 0x00000002 > +#define CONFIG_SYS_ANADIG_USB2_VBUS 0x00100004 > +#define CONFIG_SYS_ANADIG_USB2_CHRG 0x00000000 > +#define CONFIG_SYS_ANADIG_USB2_MISC 0x00000002 > +#define CONFIG_SYS_ANADIG_SYS_CTRL 0x00002001 > +#define CONFIG_SYS_ANADIG_SYS_SS 0x00000000 > +#define CONFIG_SYS_ANADIG_SYS_NUM 0x00000000 > +#define CONFIG_SYS_ANADIG_SYS_DENOM 0x00000012 > +#define CONFIG_SYS_ANADIG_SYS_PFD_528 0x00000000 > +#define CONFIG_SYS_ANADIG_SYS_PLL_LOCK 0x00000000 > + See my previous comments about this stuff. Best regards, Stefano Babic
> On 12/04/2013 08:53, Alison Wang wrote: > > This patch adds Freescale vybrid vf600 tower board support. > > > > Signed-off-by: TsiChung Liew <tsicliew@gmail.com> > > Signed-off-by: Jason Jin <Jason.jin@freescale.com> > > Signed-off-by: Alison Wang <b18965@freescale.com> > > --- > > Hi Alison. > > > board/freescale/vybrid/Makefile | 40 +++ > > board/freescale/vybrid/vybrid.c | 488 > +++++++++++++++++++++++++++++++++ > > board/freescale/vybrid/vybridimage.cfg | 44 +++ > > boards.cfg | 2 + > > include/configs/vybrid.h | 284 +++++++++++++++++++ > > include/configs/vybrid_iram.h | 284 +++++++++++++++++++ > > 6 files changed, 1142 insertions(+) > > create mode 100644 board/freescale/vybrid/Makefile create mode > > 100644 board/freescale/vybrid/vybrid.c create mode 100644 > > board/freescale/vybrid/vybridimage.cfg > > create mode 100644 include/configs/vybrid.h create mode 100644 > > include/configs/vybrid_iram.h > > > > diff --git a/board/freescale/vybrid/Makefile > > b/board/freescale/vybrid/Makefile new file mode 100644 index > > 0000000..0749b21 > > --- /dev/null > > +++ b/board/freescale/vybrid/Makefile > > @@ -0,0 +1,40 @@ > > +# > > +# Copyright 2012-2013 Freescale Semiconductor, Inc. > > +# > > +# This program is free software; you can redistribute it and/or # > > +modify it under the terms of the GNU General Public License as # > > +published by the Free Software Foundation; either version 2 of # the > > +License, or (at your option) any later version. > > +# > > +# This program is distributed in the hope that it will be useful, # > > +but WITHOUT ANY WARRANTY; without even the implied warranty of # > > +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU > > +General Public License for more details. > > +# > > +# You should have received a copy of the GNU General Public License # > > +along with this program; if not, write to the Free Software # > > +Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 > > +USA # > > + > > +include $(TOPDIR)/config.mk > > + > > +LIB = $(obj)lib$(BOARD).o > > + > > +COBJS := $(BOARD).o > > + > > +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) > > +OBJS := $(addprefix $(obj),$(COBJS)) > > +SOBJS := $(addprefix $(obj),$(SOBJS)) > > + > > +$(LIB): $(obj).depend $(OBJS) $(SOBJS) > > + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) > > + > > +##################################################################### > > +#### > > + > > +# defines $(obj).depend target > > +include $(SRCTREE)/rules.mk > > + > > +sinclude $(obj).depend > > + > > +##################################################################### > > +#### > > diff --git a/board/freescale/vybrid/vybrid.c > > b/board/freescale/vybrid/vybrid.c new file mode 100644 index > > 0000000..c2da1ff > > --- /dev/null > > +++ b/board/freescale/vybrid/vybrid.c > > @@ -0,0 +1,488 @@ > > +/* > > + * Copyright 2012-2013 Freescale Semiconductor, Inc. > > + * > > + * See file CREDITS for list of people who contributed to this > > + * project. > > + * > > + * This program is free software; you can redistribute it and/or > > + * modify it under the terms of the GNU General Public License as > > + * published by the Free Software Foundation; either version 2 of > > + * the License, or (at your option) any later version. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + * > > + * You should have received a copy of the GNU General Public License > > + * along with this program; if not, write to the Free Software > > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > > + * MA 02111-1307 USA > > + */ > > + > > +#include <common.h> > > +#include <asm/io.h> > > +#include <asm/fec.h> > > +#include <asm/arch/vybrid-regs.h> > > +#include <asm/arch/vybrid-pins.h> > > +#include <asm/arch/iomux.h> > > +#include <asm/errno.h> > > +#include <asm/arch/sys_proto.h> > > +#include <i2c.h> > > +#include <mmc.h> > > +#include <fsl_esdhc.h> > > +#include <usb/ehci-fsl.h> > > + > > +DECLARE_GLOBAL_DATA_PTR; > > + > > +#define DDR_IOMUX 0x00000180 > > +#define DDR_IOMUX1 0x00010180 > > + > > +#define PHY_DQ_TIMING 0x00002613 > > +#define PHY_DQS_TIMING 0x00002615 > > +#define PHY_CTRL 0x01210080 > > +#define PHY_MASTER_CTRL 0x0001012a > > +#define PHY_SLAVE_CTRL 0x00012020 > > + > > +#ifdef CONFIG_FSL_ESDHC > > +struct fsl_esdhc_cfg esdhc_cfg[2] = { > > + {CONFIG_SYS_ESDHC1_BASE, 1}, > > + {ESDHC2_BASE_ADDR, 1}, > > +}; > > +#endif > > + > > +void setup_iomux_ddr(void) > > +{ > > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A15); > > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A14); > > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A13); > > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A12); > > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A11); > > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A10); > > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A9); > > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A8); > > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A7); > > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A6); > > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A5); > > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A4); > > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A3); > > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A2); > > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A1); > > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_BA2); > > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_BA1); > > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_BA0); > > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_CAS); > > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_CKE); > > + __raw_writel(DDR_IOMUX1, IOMUXC_DDR_CLK); > > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_CS); > > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D15); > > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D14); > > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D13); > > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D12); > > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D11); > > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D10); > > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D9); > > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D8); > > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D7); > > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D6); > > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D5); > > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D4); > > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D3); > > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D2); > > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D1); > > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D0); > > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_DQM1); > > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_DQM0); > > + __raw_writel(DDR_IOMUX1, IOMUXC_DDR_DQS1); > > + __raw_writel(DDR_IOMUX1, IOMUXC_DDR_DQS0); > > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_RAS); > > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_WE); > > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_ODT1); > > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_ODT0); } > > + > > +void ddr_phy_init(void) > > +{ > > + /* phy_dq_timing_reg freq set 0 */ > > + __raw_writel(PHY_DQ_TIMING, DDR_PHY000); > > + __raw_writel(PHY_DQ_TIMING, DDR_PHY016); > > + __raw_writel(PHY_DQ_TIMING, DDR_PHY032); > > + __raw_writel(PHY_DQ_TIMING, DDR_PHY048); > > + > > + /* phy_dqs_timing_reg freq set 0 */ > > + __raw_writel(PHY_DQS_TIMING, DDR_PHY001); > > + __raw_writel(PHY_DQS_TIMING, DDR_PHY017); > > + __raw_writel(PHY_DQS_TIMING, DDR_PHY033); > > + __raw_writel(PHY_DQS_TIMING, DDR_PHY049); > > + > > + /* phy_gate_lpbk_ctrl_reg freq set 0 */ > > + __raw_writel(PHY_CTRL, DDR_PHY002); /* read delay bit21:19 */ > > + __raw_writel(PHY_CTRL, DDR_PHY018); /* phase_detect_sel bit18:16 */ > > + __raw_writel(PHY_CTRL, DDR_PHY034); /* bit lpbk_ctrl bit12 */ > > + __raw_writel(PHY_CTRL, DDR_PHY050); > > + > > + /* phy_dll_master_ctrl_reg freq set 0 */ > > + __raw_writel(PHY_MASTER_CTRL, DDR_PHY003); > > + __raw_writel(PHY_MASTER_CTRL, DDR_PHY019); > > + __raw_writel(PHY_MASTER_CTRL, DDR_PHY035); > > + __raw_writel(PHY_MASTER_CTRL, DDR_PHY051); > > + > > + /* phy_dll_slave_ctrl_reg freq set 0 */ > > + __raw_writel(PHY_SLAVE_CTRL, DDR_PHY004); > > + __raw_writel(PHY_SLAVE_CTRL, DDR_PHY020); > > + __raw_writel(PHY_SLAVE_CTRL, DDR_PHY036); > > + __raw_writel(PHY_SLAVE_CTRL, DDR_PHY052); > > + > > + __raw_writel(0x00001105, DDR_PHY050); } > > + > > +unsigned long ddr_ctrl_init(void) > > +{ > > + int dram_size, rows, cols, banks, port; > > + > > + __raw_writel(0x00000600, DDR_CR000); /* LPDDR2 or DDR3 */ > > + __raw_writel(0x00000020, DDR_CR002); /* TINIT */ > > + __raw_writel(0x0000007c, DDR_CR010); /* reset during power on > */ > > + /* warm boot - 200ns */ > > + __raw_writel(0x00013880, DDR_CR011); /* 500us - 10ns */ > > + __raw_writel(0x0000050c, DDR_CR012); /* CASLAT_LIN, WRLAT */ > > + __raw_writel(0x15040404, DDR_CR013); /* trc, trrd, tccd > > + tbst_int_interval */ > > + __raw_writel(0x1406040F, DDR_CR014); /* tfaw, tfp, twtr, > tras_min */ > > + __raw_writel(0x04040000, DDR_CR016); /* tmrd, trtp */ > > + __raw_writel(0x006DB00C, DDR_CR017); /* tras_max, tmod */ > > + __raw_writel(0x00000403, DDR_CR018); /* tckesr, tcke */ > > + > > + __raw_writel(0x01000000, DDR_CR020); /* ap, writrp */ > > + __raw_writel(0x06060101, DDR_CR021); /* trcd_int, tras_lockout > > + ccAP */ > > + __raw_writel(0x000B0000, DDR_CR022); /* tdal */ > > + __raw_writel(0x03000200, DDR_CR023); /* bstlen, tmrr, tdll */ > > + __raw_writel(0x00000006, DDR_CR024); /* addr_mirror, reg_dimm > > + trp_ab */ > > + __raw_writel(0x00010000, DDR_CR025); /* tref_enable, > auto_refresh > > + arefresh */ > > + __raw_writel(0x0C28002C, DDR_CR026); /* tref, trfc */ > > + __raw_writel(0x00000005, DDR_CR028); /* tref_interval fixed at > 5 */ > > + __raw_writel(0x00000003, DDR_CR029); /* tpdex */ > > + > > + __raw_writel(0x0000000A, DDR_CR030); /* txpdll */ > > + __raw_writel(0x00440200, DDR_CR031); /* txsnr, txsr */ > > + __raw_writel(0x00010000, DDR_CR033); /* cke_dly, > en_quick_srefresh > > + * srefresh_exit_no_refresh, > > + * pwr, srefresh_exit > > + */ > > + __raw_writel(0x00050500, DDR_CR034); /* cksrx, */ > > + /* cksre, lowpwr_ref_en */ > > + > > + /* Frequency change */ > > + __raw_writel(0x00000100, DDR_CR038); /* freq change... */ > > + __raw_writel(0x04001002, DDR_CR039); > > + > > + __raw_writel(0x00000001, DDR_CR041); /* dfi_init_start */ > > + __raw_writel(0x00000000, DDR_CR045); /* wrmd */ > > + __raw_writel(0x00000000, DDR_CR046); /* rdmd */ > > + __raw_writel(0x00000000, DDR_CR047); /* REF_PER_AUTO_TEMPCHK: > > + * LPDDR2 set to 2, else 0 > > + */ > > + > > + /* DRAM device Mode registers */ > > + __raw_writel(0x00460420, DDR_CR048); /* mr0, ddr3 burst of 8 > only > > + * mr1, if freq < 125 > > + * dll_dis = 1, rtt = 0 > > + * if freq > 125, dll_dis = 0 > > + * rtt = 3 > > + */ > > + __raw_writel(0x00000000, DDR_CR049); /* mr2 */ > > + __raw_writel(0x00000000, DDR_CR051); /* mr3 & mrsingle_data_0 > */ > > + > > + __raw_writel(0x00000000, DDR_CR057); /* ctrl_raw */ > > + > > + /* ZQ stuff */ > > + __raw_writel(0x01000200, DDR_CR066); /* zqcl, zqinit */ > > + __raw_writel(0x02000040, DDR_CR067); /* zqcs */ > > + __raw_writel(0x00000200, DDR_CR069); /* zq_on_sref_exit, > qz_req */ > > + > > + __raw_writel(0x00000040, DDR_CR070); /* ref_per_zq */ > > + __raw_writel(0x00000000, DDR_CR071); /* zqreset, ddr3 set to 0 > */ > > + __raw_writel(0x01000000, DDR_CR072); /* zqcs_rotate, > no_zq_init */ > > + > > + /* DRAM controller misc */ > > + __raw_writel(0x0a010300, DDR_CR073); /* arebit, col_diff, > row_diff > > + bank_diff */ > > + __raw_writel(0x0101ffff, DDR_CR074); /* bank_split, > addr_cmp_en > > + cmd/age cnt */ > > + __raw_writel(0x01010101, DDR_CR075); /* rw same pg, rw same en > > + pri en, plen */ > > + __raw_writel(0x03030101, DDR_CR076); /* #q_entries_act_dis > > + * (#cmdqueues > > + * dis_rw_grp_w_bnk_conflict > > + * w2r_split_en, cs_same_en */ > > + __raw_writel(0x01000101, DDR_CR077); /* cs_map, > inhibit_dram_cmd > > + * dis_interleave, swen */ > > + __raw_writel(0x0000000C, DDR_CR078); /* qfull, lpddr2_s4, > reduc > > + burst_on_fly */ > > + __raw_writel(0x01000000, DDR_CR079); /* ctrlupd_req_per aref > en > > + * ctrlupd_req > > + * ctrller busy > > + * in_ord_accept */ > > + /* disable interrupts */ > > + __raw_writel(0x1FFFFFFF, DDR_CR082); > > + > > + /* ODT */ > > + __raw_writel(0x01010000, DDR_CR087); /* odt: wr_map_cs0 > > + * rd_map_cs0 > > + * port_data_err_id */ > > + __raw_writel(0x00040000, DDR_CR088); /* todtl_2cmd */ > > + __raw_writel(0x00000002, DDR_CR089); /* add_odt stuff */ > > + > > + __raw_writel(0x00020000, DDR_CR091); > > + __raw_writel(0x00000000, DDR_CR092); /* tdqsck _min, max */ > > + > > + __raw_writel(0x00002819, DDR_CR096); /* wlmrd, wldqsen */ > > + > > + /* AXI ports */ > > + __raw_writel(0x00202000, DDR_CR105); > > + __raw_writel(0x20200000, DDR_CR106); > > + __raw_writel(0x00002020, DDR_CR110); > > + __raw_writel(0x00202000, DDR_CR114); > > + __raw_writel(0x20200000, DDR_CR115); > > + > > + __raw_writel(0x00000101, DDR_CR117); /* FIFO type (0-async, 1- > 2:1 > > + * 2-1:2, 3- sync, w_pri > > + * r_pri > > + */ > > + __raw_writel(0x01010000, DDR_CR118); /* w_pri, rpri, en */ > > + __raw_writel(0x00000000, DDR_CR119); /* fifo_type */ > > + > > + __raw_writel(0x02020000, DDR_CR120); > > + __raw_writel(0x00000202, DDR_CR121); > > + __raw_writel(0x01010064, DDR_CR122); > > + __raw_writel(0x00000101, DDR_CR123); > > + __raw_writel(0x00000064, DDR_CR124); > > + > > + /* TDFI */ > > + __raw_writel(0x00000000, DDR_CR125); > > + __raw_writel(0x00000B00, DDR_CR126); /* PHY rdlat */ > > + __raw_writel(0x00000000, DDR_CR127); /* dram ck dis */ > > + > > + __raw_writel(0x00000000, DDR_CR131); > > + __raw_writel(0x00000506, DDR_CR132); /* wrlat, rdlat */ > > + __raw_writel(0x02000000, DDR_CR137); > > + __raw_writel(0x04070303, DDR_CR139); > > + > > + __raw_writel(0x00000000, DDR_CR136); > > + > > + __raw_writel(0x68200000, DDR_CR154); > > + __raw_writel(0x00000202, DDR_CR155); /* pad_ibe, _sel */ > > + __raw_writel(0x00000006, DDR_CR158); /* twr */ > > + __raw_writel(0x00000006, DDR_CR159); /* todth */ > > + > > + ddr_phy_init(); > > + > > + __raw_writel(0x00000601, DDR_CR000); /* LPDDR2 or DDR3, start > */ > > + > > + udelay(200); > > + > > + rows = (__raw_readl(DDR_CR001) & 0x1F) - > > + ((__raw_readl(DDR_CR073) >> 8) & 3); > > + cols = ((__raw_readl(DDR_CR001) >> 8) & 0xF) - > > + ((__raw_readl(DDR_CR073) >> 16) & 7); > > + banks = 1 << (3 - (__raw_readl(DDR_CR073) & 3)); > > + port = ((__raw_readl(DDR_CR078) >> 8) & 1) ? 1 : 2; > > + > > + dram_size = (1 << (rows + cols)) * banks * port; > > + > > + return dram_size; > > +} > > + > > +int dram_init(void) > > +{ > > + setup_iomux_ddr(); > > +#ifdef CONFIG_SYS_UBOOT_IN_GPURAM > > + gd->ram_size = 0x80000; > > + ddr_ctrl_init(); > > +#else > > + gd->ram_size = ddr_ctrl_init(); > > +#endif > > + return 0; > > +} > > + > > +void setup_iomux_uart(void) > > +{ > > + __raw_writel(0x002011a2, IOMUXC_PAD_026); > > + __raw_writel(0x002011a1, IOMUXC_PAD_027); > > + __raw_writel(0x002011a2, IOMUXC_PAD_028); > > + __raw_writel(0x002011a1, IOMUXC_PAD_029); > > + __raw_writel(0x001011a2, IOMUXC_PAD_032); > > + __raw_writel(0x001011a1, IOMUXC_PAD_033); } > > + > > +#ifdef CONFIG_CMD_NET > > +int fecpin_setclear(struct eth_device *dev, int setclear) { > > + struct fec_info_s *info = (struct fec_info_s *)dev->priv; > > + > > + __raw_writel(0x00203191, IOMUXC_PAD_000); /* RMII_CLK */ > > + > > + if (setclear) { > > + if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { > > + __raw_writel(0x00103192, IOMUXC_PAD_045); /*MDC*/ > > + __raw_writel(0x00103193, IOMUXC_PAD_046); /*MDIO*/ > > + __raw_writel(0x00103191, IOMUXC_PAD_047); /*RxDV*/ > > + __raw_writel(0x00103191, IOMUXC_PAD_048); /*RxD1*/ > > + __raw_writel(0x00103191, IOMUXC_PAD_049); /*RxD0*/ > > + __raw_writel(0x00103191, IOMUXC_PAD_050); /*RxER*/ > > + __raw_writel(0x00103192, IOMUXC_PAD_051); /*TxD1*/ > > + __raw_writel(0x00103192, IOMUXC_PAD_052); /*TxD0*/ > > + __raw_writel(0x00103192, IOMUXC_PAD_053); /*TxEn*/ > > + } > > + if (info->iobase == CONFIG_SYS_FEC1_IOBASE) { > > + __raw_writel(0x00103192, IOMUXC_PAD_054); /*MDC*/ > > + __raw_writel(0x00103193, IOMUXC_PAD_055); /*MDIO*/ > > + __raw_writel(0x00103191, IOMUXC_PAD_056); /*RxDV*/ > > + __raw_writel(0x00103191, IOMUXC_PAD_057); /*RxD1*/ > > + __raw_writel(0x00103191, IOMUXC_PAD_058); /*RxD0*/ > > + __raw_writel(0x00103191, IOMUXC_PAD_059); /*RxER*/ > > + __raw_writel(0x00103192, IOMUXC_PAD_060); /*TxD1*/ > > + __raw_writel(0x00103192, IOMUXC_PAD_061); /*TxD0*/ > > + __raw_writel(0x00103192, IOMUXC_PAD_062); /*TxEn*/ > > + } > > + } else { > > + if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { > > + __raw_writel(0x00003192, IOMUXC_PAD_045); /*MDC*/ > > + __raw_writel(0x00003193, IOMUXC_PAD_046); /*MDIO*/ > > + __raw_writel(0x00003191, IOMUXC_PAD_047); /*RxDV*/ > > + __raw_writel(0x00003191, IOMUXC_PAD_048); /*RxD1*/ > > + __raw_writel(0x00003191, IOMUXC_PAD_049); /*RxD0*/ > > + __raw_writel(0x00003191, IOMUXC_PAD_050); /*RxER*/ > > + __raw_writel(0x00003192, IOMUXC_PAD_051); /*TxD1*/ > > + __raw_writel(0x00003192, IOMUXC_PAD_052); /*TxD0*/ > > + __raw_writel(0x00003192, IOMUXC_PAD_053); /*TxEn*/ > > + } > > + if (info->iobase == CONFIG_SYS_FEC1_IOBASE) { > > + __raw_writel(0x00003192, IOMUXC_PAD_054); /*MDC*/ > > + __raw_writel(0x00003193, IOMUXC_PAD_055); /*MDIO*/ > > + __raw_writel(0x00003191, IOMUXC_PAD_056); /*RxDV*/ > > + __raw_writel(0x00003191, IOMUXC_PAD_057); /*RxD1*/ > > + __raw_writel(0x00003191, IOMUXC_PAD_058); /*RxD0*/ > > + __raw_writel(0x00003191, IOMUXC_PAD_059); /*RxER*/ > > + __raw_writel(0x00003192, IOMUXC_PAD_060); /*TxD1*/ > > + __raw_writel(0x00003192, IOMUXC_PAD_061); /*TxD0*/ > > + __raw_writel(0x00003192, IOMUXC_PAD_062); /*TxEn*/ > > + } > > + } > > + > > + return 0; > > +} > > +#endif > > + > > +#ifdef CONFIG_QUAD_SPI > > +void setup_iomux_quadspi(void) > > +{ > > + __raw_writel(0x001030C3, IOMUXC_PAD_079); /* SCK */ > > + __raw_writel(0x001030FF, IOMUXC_PAD_080); /* CS0 */ > > + __raw_writel(0x001030C3, IOMUXC_PAD_081); /* D3 */ > > + __raw_writel(0x001030C3, IOMUXC_PAD_082); /* D2 */ > > + __raw_writel(0x001030C3, IOMUXC_PAD_083); /* D1 */ > > + __raw_writel(0x001030C3, IOMUXC_PAD_084); /* D0 */ > > + > > + __raw_writel(0x001030C3, IOMUXC_PAD_086); /* SCK */ > > + __raw_writel(0x001030FF, IOMUXC_PAD_087); /* CS0 */ > > + __raw_writel(0x001030C3, IOMUXC_PAD_088); /* D3 */ > > + __raw_writel(0x001030C3, IOMUXC_PAD_089); /* D2 */ > > + __raw_writel(0x001030C3, IOMUXC_PAD_090); /* D1 */ > > + __raw_writel(0x001030C3, IOMUXC_PAD_091); /* D0 */ > > +} > > +#endif > > + > > +#ifdef CONFIG_FSL_ESDHC > > +int board_mmc_getcd(struct mmc *mmc) > > +{ > > + int ret; > > + > > + __raw_writel(0x005031ef, IOMUXC_PAD_014); /* clk */ > > + __raw_writel(0x005031ef, IOMUXC_PAD_015); /* cmd */ > > + __raw_writel(0x005031ef, IOMUXC_PAD_016); /* dat0 */ > > + __raw_writel(0x005031ef, IOMUXC_PAD_017); /* dat1 */ > > + __raw_writel(0x005031ef, IOMUXC_PAD_018); /* dat2 */ > > + __raw_writel(0x005031ef, IOMUXC_PAD_019); /* dat3 */ > > + > > + ret = 1; > > + return ret; > > +} > > + > > +int board_mmc_init(bd_t *bis) > > +{ > > + u32 index = 0; > > + s32 status = 0; > > + > > + esdhc_cfg[0].sdhc_clk = 132000000; > > + esdhc_cfg[1].sdhc_clk = 132000000; > > + status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]); > > + return status; > > +} > > +#endif > > + > > +#ifdef CONFIG_NAND_FSL_NFC > > +void setup_iomux_nfc(void) > > +{ > > + __raw_writel(0x002038df, IOMUXC_PAD_063); > > + __raw_writel(0x002038df, IOMUXC_PAD_064); > > + __raw_writel(0x002038df, IOMUXC_PAD_065); > > + __raw_writel(0x002038df, IOMUXC_PAD_066); > > + __raw_writel(0x002038df, IOMUXC_PAD_067); > > + __raw_writel(0x002038df, IOMUXC_PAD_068); > > + __raw_writel(0x002038df, IOMUXC_PAD_069); > > + __raw_writel(0x002038df, IOMUXC_PAD_070); > > + __raw_writel(0x002038df, IOMUXC_PAD_071); > > + __raw_writel(0x002038df, IOMUXC_PAD_072); > > + __raw_writel(0x002038df, IOMUXC_PAD_073); > > + __raw_writel(0x002038df, IOMUXC_PAD_074); > > + __raw_writel(0x002038df, IOMUXC_PAD_075); > > + __raw_writel(0x002038df, IOMUXC_PAD_076); > > + __raw_writel(0x002038df, IOMUXC_PAD_077); > > + __raw_writel(0x002038df, IOMUXC_PAD_078); > > + > > + __raw_writel(0x005038d2, IOMUXC_PAD_094); > > + __raw_writel(0x005038d2, IOMUXC_PAD_095); > > + __raw_writel(0x006038d2, IOMUXC_PAD_097); > > + __raw_writel(0x005038dd, IOMUXC_PAD_099); > > + __raw_writel(0x006038d2, IOMUXC_PAD_100); > > + __raw_writel(0x006038d2, IOMUXC_PAD_101); } #endif > > + > > +int board_early_init_f(void) > > +{ > > + setup_iomux_uart(); > > +#ifdef CONFIG_NAND_FSL_NFC > > + setup_iomux_nfc(); > > +#endif > > + return 0; > > +} > > + > > +int board_init(void) > > +{ > > + /* address of boot parameters */ > > + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; > > + > > + return 0; > > +} > > + > > +#ifdef CONFIG_BOARD_LATE_INIT > > +int board_late_init(void) > > +{ > > +#ifdef CONFIG_MXC_SPI > > + setup_iomux_spi(); > > +#endif > > + return 0; > > +} > > +#endif > > + > > +int checkboard(void) > > +{ > > + puts("Board: Vybrid\n"); > > + > > + return 0; > > +} > > diff --git a/board/freescale/vybrid/vybridimage.cfg > > b/board/freescale/vybrid/vybridimage.cfg > > new file mode 100644 > > index 0000000..5da5659 > > --- /dev/null > > +++ b/board/freescale/vybrid/vybridimage.cfg > > @@ -0,0 +1,44 @@ > > +# > > +# Copyright 2012-2013 Freescale Semiconductor, Inc. > > +# > > +# See file CREDITS for list of people who contributed to this # > > +project. > > +# > > +# This program is free software; you can redistribute it and/or # > > +modify it under the terms of the GNU General Public License as # > > +published by the Free Software Foundation; either version 2 of # the > > +License or (at your option) any later version. > > +# > > +# This program is distributed in the hope that it will be useful, # > > +but WITHOUT ANY WARRANTY; without even the implied warranty of # > > +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU > > +General Public License for more details. > > +# > > +# You should have received a copy of the GNU General Public License # > > +along with this program; if not write to the Free Software # > > +Foundation Inc. 51 Franklin Street Fifth Floor Boston, # MA > > +02110-1301 USA # # Refer docs/README.imxmage for more details about > > +how-to configure # and create imximage boot image # # The syntax is > > +taken as close as possible with the kwbimage > > + > > +IMAGE_VERSION 2 > > + > > +# Boot Device : one of > > +# spi, sd (the board has no nand neither onenand) > > + > > +BOOT_FROM sd > > + > > +# Device Configuration Data (DCD) > > +# > > +# Each entry must have the format: > > +# Addr-type Address Value > > +# > > +# where: > > +# Addr-type register length (1,2 or 4 bytes) > > +# Address absolute address of the register > > +# value value to be stored in the register > > + > > +# Setting IOMUXC > > diff --git a/boards.cfg b/boards.cfg > > index 7725a15..2700a76 100644 > > --- a/boards.cfg > > +++ b/boards.cfg > > @@ -244,6 +244,8 @@ am335x_evm_uart5 arm armv7 > am335x ti > > am335x_evm_usbspl arm armv7 am335x > ti am33xx > am335x_evm:SERIAL1,CONS_INDEX=1,SPL_USBETH_SUPPORT > > pcm051 arm armv7 pcm051 > phytec am33xx pcm051 > > highbank arm armv7 highbank > - highbank > > +vybrid arm armv7 vybrid > freescale vybrid > vybrid:VYBRID_CONFIG=board/freescale/vybrid/vybridimage.cfg > > +vybrid_iram arm armv7 vybrid > freescale vybrid > vybrid_iram:VYBRID_CONFIG=board/freescale/vybrid/vybridimage.cfg > > mx51_efikamx arm armv7 mx51_efikamx > genesi mx5 > mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/gene > si/mx51_efikamx/imximage_mx.cfg > > mx51_efikasb arm armv7 mx51_efikamx > genesi mx5 > mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/gene > si/mx51_efikamx/imximage_sb.cfg > > mx51evk arm armv7 mx51evk > freescale mx5 > mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg > > diff --git a/include/configs/vybrid.h b/include/configs/vybrid.h new > > file mode 100644 index 0000000..d915bd0 > > --- /dev/null > > +++ b/include/configs/vybrid.h > > @@ -0,0 +1,284 @@ > > +/* > > + * Copyright 2012-2013 Freescale Semiconductor, Inc. > > + * > > + * Configuration settings for the vybrid Board > > + * > > + * This program is free software; you can redistribute it and/or > > + * modify it under the terms of the GNU General Public License as > > + * published by the Free Software Foundation; either version 2 of > > + * the License, or (at your option) any later version. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + * > > + * You should have received a copy of the GNU General Public License > > + * along with this program; if not, write to the Free Software > > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > > + * MA 02111-1307 USA > > + */ > > + > > +#ifndef __CONFIG_H > > +#define __CONFIG_H > > + > > + /* High Level Configuration Options */ > > + > > +#define CONFIG_VYBRID > > + > > +#define CONFIG_SYS_VYBRID_HCLK 24000000 > > +#define CONFIG_SYS_VYBRID_CLK32 32768 > > +#define CONFIG_DISPLAY_CPUINFO > > +#define CONFIG_DISPLAY_BOARDINFO > > +#define CONFIG_SYS_IPG > > + > > +#define CONFIG_SYS_ICACHE_OFF > > +#define CONFIG_SYS_CACHELINE_SIZE 64 > > + > > +#include <asm/arch/vybrid-regs.h> > > + > > +/* > > + * Disabled for now due to build problems under Debian and a > > +significant > > + * increase in the final file size: 144260 vs. 109536 Bytes. > > + */ > > + > > +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ > > +#undef CONFIG_SETUP_MEMORY_TAGS > > +#undef CONFIG_INITRD_TAG > > + > > +#undef CONFIG_OF_LIBFDT > > + > > +#define CONFIG_MACH_TYPE MACH_TYPE_VYBRID_VF6XX > > +/* Size of malloc() pool */ > > +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * > 1024) > > + > > +#define CONFIG_BOARD_LATE_INIT > > + > > +/* Hardware drivers */ > > +#define CONFIG_VYBRID_UART > > +#define CONFIG_VYBRID_UART_BASE UART0_BASE > > +#define CONFIG_VYBRID_GPIO > > + > > +/* allow to overwrite serial and ethaddr */ #define > > +CONFIG_ENV_OVERWRITE > > +#define CONFIG_SYS_UART_PORT (1) > > +#define CONFIG_BAUDRATE 115200 > > +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, > 115200} > > + > > +/* Command definition */ > > +#include <config_cmd_default.h> > > + > > +#define CONFIG_CMD_BDI /* bdinfo */ > > +#define CONFIG_CMD_BOOTD > > +#define CONFIG_CMD_CONSOLE /* coninfo */ > > +#define CONFIG_CMD_DHCP > > +#define CONFIG_CMD_ELF > > +#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest > */ > > +#define CONFIG_CMD_MISC > > +#define CONFIG_CMD_MII > > +#define CONFIG_CMD_NET > > +#undef CONFIG_CMD_NFS /* NFS support */ > > +#define CONFIG_CMD_PING > > +#undef CONFIG_CMD_NAND > > +#undef CONFIG_CMD_DATE > > +#undef CONFIG_CMD_IMI /* iminfo */ > > +#undef CONFIG_CMD_IMLS > > +#undef CONFIG_CMD_LOADB /* loadb */ > > +#undef CONFIG_CMD_LOADS /* loads */ > > + > > +#define CONFIG_SYS_TEXT_BASE 0x3f000800 > > + > > +#define CONFIG_MMC > > +#ifdef CONFIG_MMC > > +#define CONFIG_SYS_ESDHC1_BASE ESDHC2_BASE_ADDR > > +#define CONFIG_SYS_ESDHC2_BASE ESDHC2_BASE_ADDR > > +#define CONFIG_FSL_ESDHC > > +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 > > +#define CONFIG_SYS_FSL_ESDHC_NUM 1 > > + > > +#define CONFIG_SYS_FSL_ERRATUM_ESDHC135 #define > > +CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define > > +CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 > > + > > +#define CONFIG_CMD_MMC > > +#define CONFIG_GENERIC_MMC > > +#define CONFIG_CMD_FAT > > +#define CONFIG_DOS_PARTITION > > +#endif > > + > > +/* > > + * NAND FLASH > > + */ > > +#ifdef CONFIG_CMD_NAND > > +#define CONFIG_MTD_NAND_FSL_NFC_SWECC 1 > > +#define CONFIG_JFFS2_NAND > > +#define CONFIG_NAND_FSL_NFC > > +#define CONFIG_SYS_NAND_BASE 0x400E0000 > > +#define CONFIG_SYS_MAX_NAND_DEVICE 1 > > +#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE > > +#define CONFIG_SYS_NAND_SELECT_DEVICE > > +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ > > +#endif > > + > > +#define CONFIG_QUAD_SPI > > + > > +/* Network configuration */ > > +#define CONFIG_MCFFEC > > +#ifdef CONFIG_MCFFEC > > +# define CONFIG_MII 1 > > +# define CONFIG_MII_INIT 1 > > +# define CONFIG_SYS_DISCOVER_PHY > > +# define CONFIG_SYS_RX_ETH_BUFFER 8 > > +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN > > + > > +# define CONFIG_SYS_FEC0_PINMUX 0 > > +# define CONFIG_SYS_FEC1_PINMUX 0 > > +# define CONFIG_SYS_FEC0_IOBASE MACNET0_BASE_ADDR > > +# define CONFIG_SYS_FEC1_IOBASE MACNET1_BASE_ADDR > > +# define CONFIG_SYS_FEC0_MIIBASE MACNET0_BASE_ADDR > > +# define CONFIG_SYS_FEC1_MIIBASE MACNET0_BASE_ADDR > > +# define MCFFEC_TOUT_LOOP 50000 > > +# undef CONFIG_HAS_ETH1 > > + > > +# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 > > +# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61 > > +# define CONFIG_ETHPRIME "FEC0" > > +# define CONFIG_IPADDR 10.81.67.175 > > +# define CONFIG_NETMASK 255.255.252.0 > > +# define CONFIG_SERVERIP 10.81.64.153 > > +# define CONFIG_GATEWAYIP 10.81.67.254 > > +# define CONFIG_OVERWRITE_ETHADDR_ONCE > > + > > +/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ > > +# ifndef CONFIG_SYS_DISCOVER_PHY > > +# define FECDUPLEX FULL > > +# define FECSPEED _100BASET > > +# else > > +# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN > > +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN > > +# endif > > +# endif /* CONFIG_SYS_DISCOVER_PHY */ > > +#endif > > + > > +#define CONFIG_BOOTDELAY 3 > > +#define CONFIG_ETHPRIME "FEC0" > > +#define CONFIG_LOADADDR 0x80010000 /* loadaddr env var > */ > > +#define CONFIG_ARP_TIMEOUT 200UL > > + > > +/* Miscellaneous configurable options */ > > +#define CONFIG_SYS_LONGHELP /* undef to save memory */ > > +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ > > +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " > > +#define CONFIG_SYS_PROMPT "Vybrid U-Boot > " > > +#undef CONFIG_AUTO_COMPLETE > > +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ > > +/* Print Buffer Size */ > > +#define CONFIG_SYS_PBSIZE \ > > + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) > > +#define CONFIG_SYS_MAXARGS 16 /* max number of command args > */ > > +/* Boot Argument Buffer Size */ > > +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE > > + > > +#define CONFIG_SYS_MEMTEST_START 0x80010000 > > +#define CONFIG_SYS_MEMTEST_END 0x87C00000 > > + > > +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR > > + > > +#define CONFIG_SYS_HZ 1000 > > +#undef CONFIG_CMDLINE_EDITING > > + > > +#define CONFIG_PRAM 2048 > > + > > +/* > > + * Stack sizes > > + * The stack sizes are set up in start.S using the settings below */ > > +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ > > + > > +/* Physical Memory Map */ > > +#define CONFIG_NR_DRAM_BANKS 1 > > +#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) > > + > > +#define CONFIG_SYS_SDRAM_BASE (0x80000000) > > +#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) > > +#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) > > + > > +#define CONFIG_BOARD_EARLY_INIT_F > > + > > +#define CONFIG_SYS_INIT_SP_OFFSET \ > > + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define > > +CONFIG_SYS_INIT_SP_ADDR \ > > + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) > > + > > +/* timer */ > > +#define FTM_BASE_ADDR FTM0_BASE_ADDR > > +#define CONFIG_TMR_USEPIT > > + > > +/* clock/PLL configuration */ > > +/* uart0-2 */ > > +#define CONFIG_SYS_CLKCTL_CCGR0 0x000FC000 > > +/* crc, pit, ftm0/1, a5/m4 wdog */ > > +#define CONFIG_SYS_CLKCTL_CCGR1 0xF00FC0C0 > > +/* lptmr, qspi0, iomuxc, gpio */ > > +#define CONFIG_SYS_CLKCTL_CCGR2 0x0FFF0303 > > +/* anadig, scscm*/ > > +#define CONFIG_SYS_CLKCTL_CCGR3 0x00000033 > > +/* acrc, i2c0/1, wkup, ccm, gpc, src */ > > +#define CONFIG_SYS_CLKCTL_CCGR4 0x33f0f003 > > +#define CONFIG_SYS_CLKCTL_CCGR5 0xFFFFFFFF > > +/* ocotp, snvs, wdog_snvs, ddrmc */ > > +#define CONFIG_SYS_CLKCTL_CCGR6 0x3003cc00 > > +/* usb1, sdhc0/1 */ > > +#define CONFIG_SYS_CLKCTL_CCGR7 0x0000033c > > +/* qspi1 */ > > +#define CONFIG_SYS_CLKCTL_CCGR8 0x00000300 > > +/* enet0/1 */ > > +#define CONFIG_SYS_CLKCTL_CCGR9 0x0000000f > > +/* nfc */ > > +#define CONFIG_SYS_CLKCTL_CCGR10 0x00000003 > > +/* caam */ > > +#define CONFIG_SYS_CLKCTL_CCGR11 0x00000003 > > + > > +#define CONFIG_SYS_CLKCTRL_CCR 0x00010005 > > +#define CONFIG_SYS_CLKCTRL_CCSR 0x0003FF64 > > +#define CONFIG_SYS_CLKCTRL_CACRR 0x00000810 > > +#define CONFIG_SYS_CLKCTRL_CSCMR1 0x03CA0000 > > +#define CONFIG_SYS_CLKCTRL_CSCDR1 0x01000000 > > +#define CONFIG_SYS_CLKCTRL_CSCDR2 0x30114240 > > +#define CONFIG_SYS_CLKCTRL_CSCDR3 0x00003F1F > > +#define CONFIG_SYS_CLKCTRL_CSCMR2 0x00000000 > > +#define CONFIG_SYS_CLKCTRL_CSCDR4 0x00000000 > > +#define CONFIG_SYS_CLKCTRL_CLPCR 0x00000078 > > + > > +#define CONFIG_SYS_ANADIG_USB1_CTRL 0x00012000 > > +#define CONFIG_SYS_ANADIG_USB2_CTRL 0x00012000 > > +#define CONFIG_SYS_ANADIG_528_CTRL 0x00002001 > > +#define CONFIG_SYS_ANADIG_528_SS 0x00000000 > > +#define CONFIG_SYS_ANADIG_528_NUM 0x00000000 > > +#define CONFIG_SYS_ANADIG_528_DENOM 0x00000012 > > +#define CONFIG_SYS_ANADIG_VID_CTRL 0x00011028 > > +#define CONFIG_SYS_ANADIG_VID_NUM 0x00000000 > > +#define CONFIG_SYS_ANADIG_VID_DENOM 0x00000012 > > +#define CONFIG_SYS_ANADIG_ENET_CTRL 0x00011001 > > +#define CONFIG_SYS_ANADIG_PFD_USB1 0x1B1D1A1C > > +#define CONFIG_SYS_ANADIG_PFD_528 0x171C1813 > > +#define CONFIG_SYS_ANADIG_USB1_MISC 0x00000002 > > +#define CONFIG_SYS_ANADIG_USB2_VBUS 0x00100004 > > +#define CONFIG_SYS_ANADIG_USB2_CHRG 0x00000000 > > +#define CONFIG_SYS_ANADIG_USB2_MISC 0x00000002 > > +#define CONFIG_SYS_ANADIG_SYS_CTRL 0x00002001 > > +#define CONFIG_SYS_ANADIG_SYS_SS 0x00000000 > > +#define CONFIG_SYS_ANADIG_SYS_NUM 0x00000000 > > +#define CONFIG_SYS_ANADIG_SYS_DENOM 0x00000012 > > +#define CONFIG_SYS_ANADIG_SYS_PFD_528 0x00000000 > > +#define CONFIG_SYS_ANADIG_SYS_PLL_LOCK 0x00000000 > > + > > +/* FLASH and environment organization */ #define CONFIG_SYS_NO_FLASH > > + > > +#define CONFIG_ENV_OFFSET (12 * 64 * 1024) > > +#define CONFIG_ENV_SIZE (8 * 1024) > > +#define CONFIG_ENV_IS_IN_MMC > > +#define CONFIG_SYS_MMC_ENV_DEV 0 > > + > > +#endif > > diff --git a/include/configs/vybrid_iram.h > > b/include/configs/vybrid_iram.h new file mode 100644 index > > 0000000..f88050e > > --- /dev/null > > +++ b/include/configs/vybrid_iram.h > > @@ -0,0 +1,284 @@ > > +/* > > + * Copyright 2013 Freescale Semiconductor, Inc. > > + * > > + * Configuration settings for the vybrid Board > > + * > > + * This program is free software; you can redistribute it and/or > > + * modify it under the terms of the GNU General Public License as > > + * published by the Free Software Foundation; either version 2 of > > + * the License, or (at your option) any later version. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + * > > + * You should have received a copy of the GNU General Public License > > + * along with this program; if not, write to the Free Software > > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > > + * MA 02111-1307 USA > > + */ > > + > > As the name suggest, I am expecting that <soc>_iram.h contains the layout > of the internal RAM, IRAM on Freescale's SOC. So the name is inconsistent > with a board name. > > > +#ifndef __CONFIG_H > > +#define __CONFIG_H > > + > > +/* High Level Configuration Options */ > > + > > +#define CONFIG_VYBRID > > + > > +#define CONFIG_SYS_VYBRID_HCLK 24000000 > > +#define CONFIG_SYS_VYBRID_CLK32 32768 > > As I have already said, each CONFIG_SYS must be documented. Anyway, we > get rid of these two defines in MX2x / MX3 /.. Do we really need them ? [Alison Wang] Agree, I will remove these two defines in the next version patches. Thanks. > > > +#define CONFIG_SYS_UBOOT_IN_GPURAM > > ??? > > > +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ > > +#undef CONFIG_SETUP_MEMORY_TAGS > > +#undef CONFIG_INITRD_TAG > > + > > +#undef CONFIG_OF_LIBFDT > > + > > +#define CONFIG_MACH_TYPE MACH_TYPE_VYBRID_VF6XX > > Set MACH_TYPE_VYBRID_VF6XX in this file [Alison Wang] Agree. Thanks. > > > +/* Command definition */ > > +#include <config_cmd_default.h> > > + > > +#define CONFIG_CMD_BDI /* bdinfo */ > > +#define CONFIG_CMD_BOOTD > > +#define CONFIG_CMD_CONSOLE /* coninfo */ > > +#define CONFIG_CMD_DHCP > > +#define CONFIG_CMD_ELF > > +#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest > */ > > +#define CONFIG_CMD_MISC > > +#define CONFIG_CMD_MII > > +#define CONFIG_CMD_NET > > +#undef CONFIG_CMD_NFS /* NFS support */ > > +#define CONFIG_CMD_PING > > +#undef CONFIG_CMD_DATE > > +#undef CONFIG_CMD_IMI /* iminfo */ > > +#undef CONFIG_CMD_IMLS > > +#undef CONFIG_CMD_LOADB /* loadb */ > > +#undef CONFIG_CMD_LOADS /* loads */ > > + > > +#define CONFIG_SYS_TEXT_BASE 0x3f000800 > > + > > +#define CONFIG_MMC > > +#ifdef CONFIG_MMC > > +#define CONFIG_SYS_ESDHC1_BASE ESDHC2_BASE_ADDR > > +#define CONFIG_SYS_ESDHC2_BASE ESDHC2_BASE_ADDR > > +#define CONFIG_FSL_ESDHC > > +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 > > +#define CONFIG_SYS_FSL_ESDHC_NUM 1 > > + > > +#define CONFIG_SYS_FSL_ERRATUM_ESDHC135 #define > > +CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define > > +CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 > > Maybe correct, but they are up now defined only in PowerPC boards. Do you > confirm that they are needed ? [Alison Wang] They are not needed. I will remove them in the next version patches. Thanks. > > > +/* > > + * NAND FLASH > > + */ > > +#ifdef CONFIG_CMD_NAND > > +#define CONFIG_JFFS2_NAND > > +#define CONFIG_NAND_FSL_NFC > > +#define CONFIG_SYS_NAND_BASE 0x400E0000 > > +#define CONFIG_SYS_MAX_NAND_DEVICE 1 > > +#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE > > +#define CONFIG_SYS_NAND_SELECT_DEVICE > > +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ > > +#endif > > Does the board have NAND ? I do not see the nand driver. [Alison Wang] I will add nand driver later. > > > > + > > +/* Network configuration */ > > +#define CONFIG_MCFFEC > > +#ifdef CONFIG_MCFFEC > > +# define CONFIG_MII 1 > > +# define CONFIG_MII_INIT 1 > > +# define CONFIG_SYS_DISCOVER_PHY > > +# define CONFIG_SYS_RX_ETH_BUFFER 8 > > +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN > > + > > +# define CONFIG_SYS_FEC0_PINMUX 0 > > +# define CONFIG_SYS_FEC1_PINMUX 0 > > +# define CONFIG_SYS_FEC0_IOBASE MACNET0_BASE_ADDR > > +# define CONFIG_SYS_FEC1_IOBASE MACNET1_BASE_ADDR > > +# define CONFIG_SYS_FEC0_MIIBASE MACNET0_BASE_ADDR > > +# define CONFIG_SYS_FEC1_MIIBASE MACNET0_BASE_ADDR > > +# define MCFFEC_TOUT_LOOP 50000 > > +# undef CONFIG_HAS_ETH1 > > + > > +# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 > > +# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61 > > Do not hardcode network addresses in u-boot [Alison Wang] Agree. Thanks. > > > +/* timer */ > > +#define FTM_BASE_ADDR FTM0_BASE_ADDR > > +#define CONFIG_TMR_USEPIT > > + > > +/* clock/PLL configuration */ > > +/* uart0-2 */ > > +#define CONFIG_SYS_CLKCTL_CCGR0 0x000FC000 > > +/* crc, pit, ftm0/1, a5/m4 wdog */ > > +#define CONFIG_SYS_CLKCTL_CCGR1 0xF00FC0C0 > > +/* lptmr, qspi0, iomuxc, gpio */ > > +#define CONFIG_SYS_CLKCTL_CCGR2 0x0FFF0303 > > +/* anadig, scscm*/ > > +#define CONFIG_SYS_CLKCTL_CCGR3 0x00000033 > > +/* acrc, i2c0/1, wkup, ccm, gpc, src */ > > +#define CONFIG_SYS_CLKCTL_CCGR4 0x33f0f003 > > +#define CONFIG_SYS_CLKCTL_CCGR5 0xFFFFFFFF > > +/* ocotp, snvs, wdog_snvs, ddrmc */ > > +#define CONFIG_SYS_CLKCTL_CCGR6 0x3003cc00 > > +/* usb1, sdhc0/1 */ > > +#define CONFIG_SYS_CLKCTL_CCGR7 0x0000033c > > +/* qspi1 */ > > +#define CONFIG_SYS_CLKCTL_CCGR8 0x00000300 > > +/* enet0/1 */ > > +#define CONFIG_SYS_CLKCTL_CCGR9 0x0000000f > > +/* nfc */ > > +#define CONFIG_SYS_CLKCTL_CCGR10 0x00000003 > > +/* caam */ > > +#define CONFIG_SYS_CLKCTL_CCGR11 0x00000003 > > + > > +#define CONFIG_SYS_CLKCTRL_CCR 0x00010005 > > +#define CONFIG_SYS_CLKCTRL_CCSR 0x0003FF64 > > +#define CONFIG_SYS_CLKCTRL_CACRR 0x00000810 > > +#define CONFIG_SYS_CLKCTRL_CSCMR1 0x03CA0000 > > +#define CONFIG_SYS_CLKCTRL_CSCDR1 0x01000000 > > +#define CONFIG_SYS_CLKCTRL_CSCDR2 0x30114240 > > +#define CONFIG_SYS_CLKCTRL_CSCDR3 0x00003F1F > > +#define CONFIG_SYS_CLKCTRL_CSCMR2 0x00000000 > > +#define CONFIG_SYS_CLKCTRL_CSCDR4 0x00000000 > > +#define CONFIG_SYS_CLKCTRL_CLPCR 0x00000078 > > + > > +#define CONFIG_SYS_ANADIG_USB1_CTRL 0x00012000 > > +#define CONFIG_SYS_ANADIG_USB2_CTRL 0x00012000 > > +#define CONFIG_SYS_ANADIG_528_CTRL 0x00002001 > > +#define CONFIG_SYS_ANADIG_528_SS 0x00000000 > > +#define CONFIG_SYS_ANADIG_528_NUM 0x00000000 > > +#define CONFIG_SYS_ANADIG_528_DENOM 0x00000012 > > +#define CONFIG_SYS_ANADIG_VID_CTRL 0x00011028 > > +#define CONFIG_SYS_ANADIG_VID_NUM 0x00000000 > > +#define CONFIG_SYS_ANADIG_VID_DENOM 0x00000012 > > +#define CONFIG_SYS_ANADIG_ENET_CTRL 0x00011001 > > +#define CONFIG_SYS_ANADIG_PFD_USB1 0x1B1D1A1C > > +#define CONFIG_SYS_ANADIG_PFD_528 0x171C1813 > > +#define CONFIG_SYS_ANADIG_USB1_MISC 0x00000002 > > +#define CONFIG_SYS_ANADIG_USB2_VBUS 0x00100004 > > +#define CONFIG_SYS_ANADIG_USB2_CHRG 0x00000000 > > +#define CONFIG_SYS_ANADIG_USB2_MISC 0x00000002 > > +#define CONFIG_SYS_ANADIG_SYS_CTRL 0x00002001 > > +#define CONFIG_SYS_ANADIG_SYS_SS 0x00000000 > > +#define CONFIG_SYS_ANADIG_SYS_NUM 0x00000000 > > +#define CONFIG_SYS_ANADIG_SYS_DENOM 0x00000012 > > +#define CONFIG_SYS_ANADIG_SYS_PFD_528 0x00000000 > > +#define CONFIG_SYS_ANADIG_SYS_PLL_LOCK 0x00000000 > > + > > See my previous comments about this stuff. [Alison Wang] Agree. > Thanks a lot! Best Regards, Alison Wang
diff --git a/board/freescale/vybrid/Makefile b/board/freescale/vybrid/Makefile new file mode 100644 index 0000000..0749b21 --- /dev/null +++ b/board/freescale/vybrid/Makefile @@ -0,0 +1,40 @@ +# +# Copyright 2012-2013 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := $(BOARD).o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/vybrid/vybrid.c b/board/freescale/vybrid/vybrid.c new file mode 100644 index 0000000..c2da1ff --- /dev/null +++ b/board/freescale/vybrid/vybrid.c @@ -0,0 +1,488 @@ +/* + * Copyright 2012-2013 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/fec.h> +#include <asm/arch/vybrid-regs.h> +#include <asm/arch/vybrid-pins.h> +#include <asm/arch/iomux.h> +#include <asm/errno.h> +#include <asm/arch/sys_proto.h> +#include <i2c.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <usb/ehci-fsl.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define DDR_IOMUX 0x00000180 +#define DDR_IOMUX1 0x00010180 + +#define PHY_DQ_TIMING 0x00002613 +#define PHY_DQS_TIMING 0x00002615 +#define PHY_CTRL 0x01210080 +#define PHY_MASTER_CTRL 0x0001012a +#define PHY_SLAVE_CTRL 0x00012020 + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg esdhc_cfg[2] = { + {CONFIG_SYS_ESDHC1_BASE, 1}, + {ESDHC2_BASE_ADDR, 1}, +}; +#endif + +void setup_iomux_ddr(void) +{ + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A15); + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A14); + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A13); + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A12); + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A11); + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A10); + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A9); + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A8); + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A7); + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A6); + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A5); + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A4); + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A3); + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A2); + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A1); + __raw_writel(DDR_IOMUX, IOMUXC_DDR_BA2); + __raw_writel(DDR_IOMUX, IOMUXC_DDR_BA1); + __raw_writel(DDR_IOMUX, IOMUXC_DDR_BA0); + __raw_writel(DDR_IOMUX, IOMUXC_DDR_CAS); + __raw_writel(DDR_IOMUX, IOMUXC_DDR_CKE); + __raw_writel(DDR_IOMUX1, IOMUXC_DDR_CLK); + __raw_writel(DDR_IOMUX, IOMUXC_DDR_CS); + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D15); + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D14); + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D13); + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D12); + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D11); + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D10); + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D9); + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D8); + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D7); + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D6); + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D5); + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D4); + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D3); + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D2); + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D1); + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D0); + __raw_writel(DDR_IOMUX, IOMUXC_DDR_DQM1); + __raw_writel(DDR_IOMUX, IOMUXC_DDR_DQM0); + __raw_writel(DDR_IOMUX1, IOMUXC_DDR_DQS1); + __raw_writel(DDR_IOMUX1, IOMUXC_DDR_DQS0); + __raw_writel(DDR_IOMUX, IOMUXC_DDR_RAS); + __raw_writel(DDR_IOMUX, IOMUXC_DDR_WE); + __raw_writel(DDR_IOMUX, IOMUXC_DDR_ODT1); + __raw_writel(DDR_IOMUX, IOMUXC_DDR_ODT0); +} + +void ddr_phy_init(void) +{ + /* phy_dq_timing_reg freq set 0 */ + __raw_writel(PHY_DQ_TIMING, DDR_PHY000); + __raw_writel(PHY_DQ_TIMING, DDR_PHY016); + __raw_writel(PHY_DQ_TIMING, DDR_PHY032); + __raw_writel(PHY_DQ_TIMING, DDR_PHY048); + + /* phy_dqs_timing_reg freq set 0 */ + __raw_writel(PHY_DQS_TIMING, DDR_PHY001); + __raw_writel(PHY_DQS_TIMING, DDR_PHY017); + __raw_writel(PHY_DQS_TIMING, DDR_PHY033); + __raw_writel(PHY_DQS_TIMING, DDR_PHY049); + + /* phy_gate_lpbk_ctrl_reg freq set 0 */ + __raw_writel(PHY_CTRL, DDR_PHY002); /* read delay bit21:19 */ + __raw_writel(PHY_CTRL, DDR_PHY018); /* phase_detect_sel bit18:16 */ + __raw_writel(PHY_CTRL, DDR_PHY034); /* bit lpbk_ctrl bit12 */ + __raw_writel(PHY_CTRL, DDR_PHY050); + + /* phy_dll_master_ctrl_reg freq set 0 */ + __raw_writel(PHY_MASTER_CTRL, DDR_PHY003); + __raw_writel(PHY_MASTER_CTRL, DDR_PHY019); + __raw_writel(PHY_MASTER_CTRL, DDR_PHY035); + __raw_writel(PHY_MASTER_CTRL, DDR_PHY051); + + /* phy_dll_slave_ctrl_reg freq set 0 */ + __raw_writel(PHY_SLAVE_CTRL, DDR_PHY004); + __raw_writel(PHY_SLAVE_CTRL, DDR_PHY020); + __raw_writel(PHY_SLAVE_CTRL, DDR_PHY036); + __raw_writel(PHY_SLAVE_CTRL, DDR_PHY052); + + __raw_writel(0x00001105, DDR_PHY050); +} + +unsigned long ddr_ctrl_init(void) +{ + int dram_size, rows, cols, banks, port; + + __raw_writel(0x00000600, DDR_CR000); /* LPDDR2 or DDR3 */ + __raw_writel(0x00000020, DDR_CR002); /* TINIT */ + __raw_writel(0x0000007c, DDR_CR010); /* reset during power on */ + /* warm boot - 200ns */ + __raw_writel(0x00013880, DDR_CR011); /* 500us - 10ns */ + __raw_writel(0x0000050c, DDR_CR012); /* CASLAT_LIN, WRLAT */ + __raw_writel(0x15040404, DDR_CR013); /* trc, trrd, tccd + tbst_int_interval */ + __raw_writel(0x1406040F, DDR_CR014); /* tfaw, tfp, twtr, tras_min */ + __raw_writel(0x04040000, DDR_CR016); /* tmrd, trtp */ + __raw_writel(0x006DB00C, DDR_CR017); /* tras_max, tmod */ + __raw_writel(0x00000403, DDR_CR018); /* tckesr, tcke */ + + __raw_writel(0x01000000, DDR_CR020); /* ap, writrp */ + __raw_writel(0x06060101, DDR_CR021); /* trcd_int, tras_lockout + ccAP */ + __raw_writel(0x000B0000, DDR_CR022); /* tdal */ + __raw_writel(0x03000200, DDR_CR023); /* bstlen, tmrr, tdll */ + __raw_writel(0x00000006, DDR_CR024); /* addr_mirror, reg_dimm + trp_ab */ + __raw_writel(0x00010000, DDR_CR025); /* tref_enable, auto_refresh + arefresh */ + __raw_writel(0x0C28002C, DDR_CR026); /* tref, trfc */ + __raw_writel(0x00000005, DDR_CR028); /* tref_interval fixed at 5 */ + __raw_writel(0x00000003, DDR_CR029); /* tpdex */ + + __raw_writel(0x0000000A, DDR_CR030); /* txpdll */ + __raw_writel(0x00440200, DDR_CR031); /* txsnr, txsr */ + __raw_writel(0x00010000, DDR_CR033); /* cke_dly, en_quick_srefresh + * srefresh_exit_no_refresh, + * pwr, srefresh_exit + */ + __raw_writel(0x00050500, DDR_CR034); /* cksrx, */ + /* cksre, lowpwr_ref_en */ + + /* Frequency change */ + __raw_writel(0x00000100, DDR_CR038); /* freq change... */ + __raw_writel(0x04001002, DDR_CR039); + + __raw_writel(0x00000001, DDR_CR041); /* dfi_init_start */ + __raw_writel(0x00000000, DDR_CR045); /* wrmd */ + __raw_writel(0x00000000, DDR_CR046); /* rdmd */ + __raw_writel(0x00000000, DDR_CR047); /* REF_PER_AUTO_TEMPCHK: + * LPDDR2 set to 2, else 0 + */ + + /* DRAM device Mode registers */ + __raw_writel(0x00460420, DDR_CR048); /* mr0, ddr3 burst of 8 only + * mr1, if freq < 125 + * dll_dis = 1, rtt = 0 + * if freq > 125, dll_dis = 0 + * rtt = 3 + */ + __raw_writel(0x00000000, DDR_CR049); /* mr2 */ + __raw_writel(0x00000000, DDR_CR051); /* mr3 & mrsingle_data_0 */ + + __raw_writel(0x00000000, DDR_CR057); /* ctrl_raw */ + + /* ZQ stuff */ + __raw_writel(0x01000200, DDR_CR066); /* zqcl, zqinit */ + __raw_writel(0x02000040, DDR_CR067); /* zqcs */ + __raw_writel(0x00000200, DDR_CR069); /* zq_on_sref_exit, qz_req */ + + __raw_writel(0x00000040, DDR_CR070); /* ref_per_zq */ + __raw_writel(0x00000000, DDR_CR071); /* zqreset, ddr3 set to 0 */ + __raw_writel(0x01000000, DDR_CR072); /* zqcs_rotate, no_zq_init */ + + /* DRAM controller misc */ + __raw_writel(0x0a010300, DDR_CR073); /* arebit, col_diff, row_diff + bank_diff */ + __raw_writel(0x0101ffff, DDR_CR074); /* bank_split, addr_cmp_en + cmd/age cnt */ + __raw_writel(0x01010101, DDR_CR075); /* rw same pg, rw same en + pri en, plen */ + __raw_writel(0x03030101, DDR_CR076); /* #q_entries_act_dis + * (#cmdqueues + * dis_rw_grp_w_bnk_conflict + * w2r_split_en, cs_same_en */ + __raw_writel(0x01000101, DDR_CR077); /* cs_map, inhibit_dram_cmd + * dis_interleave, swen */ + __raw_writel(0x0000000C, DDR_CR078); /* qfull, lpddr2_s4, reduc + burst_on_fly */ + __raw_writel(0x01000000, DDR_CR079); /* ctrlupd_req_per aref en + * ctrlupd_req + * ctrller busy + * in_ord_accept */ + /* disable interrupts */ + __raw_writel(0x1FFFFFFF, DDR_CR082); + + /* ODT */ + __raw_writel(0x01010000, DDR_CR087); /* odt: wr_map_cs0 + * rd_map_cs0 + * port_data_err_id */ + __raw_writel(0x00040000, DDR_CR088); /* todtl_2cmd */ + __raw_writel(0x00000002, DDR_CR089); /* add_odt stuff */ + + __raw_writel(0x00020000, DDR_CR091); + __raw_writel(0x00000000, DDR_CR092); /* tdqsck _min, max */ + + __raw_writel(0x00002819, DDR_CR096); /* wlmrd, wldqsen */ + + /* AXI ports */ + __raw_writel(0x00202000, DDR_CR105); + __raw_writel(0x20200000, DDR_CR106); + __raw_writel(0x00002020, DDR_CR110); + __raw_writel(0x00202000, DDR_CR114); + __raw_writel(0x20200000, DDR_CR115); + + __raw_writel(0x00000101, DDR_CR117); /* FIFO type (0-async, 1-2:1 + * 2-1:2, 3- sync, w_pri + * r_pri + */ + __raw_writel(0x01010000, DDR_CR118); /* w_pri, rpri, en */ + __raw_writel(0x00000000, DDR_CR119); /* fifo_type */ + + __raw_writel(0x02020000, DDR_CR120); + __raw_writel(0x00000202, DDR_CR121); + __raw_writel(0x01010064, DDR_CR122); + __raw_writel(0x00000101, DDR_CR123); + __raw_writel(0x00000064, DDR_CR124); + + /* TDFI */ + __raw_writel(0x00000000, DDR_CR125); + __raw_writel(0x00000B00, DDR_CR126); /* PHY rdlat */ + __raw_writel(0x00000000, DDR_CR127); /* dram ck dis */ + + __raw_writel(0x00000000, DDR_CR131); + __raw_writel(0x00000506, DDR_CR132); /* wrlat, rdlat */ + __raw_writel(0x02000000, DDR_CR137); + __raw_writel(0x04070303, DDR_CR139); + + __raw_writel(0x00000000, DDR_CR136); + + __raw_writel(0x68200000, DDR_CR154); + __raw_writel(0x00000202, DDR_CR155); /* pad_ibe, _sel */ + __raw_writel(0x00000006, DDR_CR158); /* twr */ + __raw_writel(0x00000006, DDR_CR159); /* todth */ + + ddr_phy_init(); + + __raw_writel(0x00000601, DDR_CR000); /* LPDDR2 or DDR3, start */ + + udelay(200); + + rows = (__raw_readl(DDR_CR001) & 0x1F) - + ((__raw_readl(DDR_CR073) >> 8) & 3); + cols = ((__raw_readl(DDR_CR001) >> 8) & 0xF) - + ((__raw_readl(DDR_CR073) >> 16) & 7); + banks = 1 << (3 - (__raw_readl(DDR_CR073) & 3)); + port = ((__raw_readl(DDR_CR078) >> 8) & 1) ? 1 : 2; + + dram_size = (1 << (rows + cols)) * banks * port; + + return dram_size; +} + +int dram_init(void) +{ + setup_iomux_ddr(); +#ifdef CONFIG_SYS_UBOOT_IN_GPURAM + gd->ram_size = 0x80000; + ddr_ctrl_init(); +#else + gd->ram_size = ddr_ctrl_init(); +#endif + return 0; +} + +void setup_iomux_uart(void) +{ + __raw_writel(0x002011a2, IOMUXC_PAD_026); + __raw_writel(0x002011a1, IOMUXC_PAD_027); + __raw_writel(0x002011a2, IOMUXC_PAD_028); + __raw_writel(0x002011a1, IOMUXC_PAD_029); + __raw_writel(0x001011a2, IOMUXC_PAD_032); + __raw_writel(0x001011a1, IOMUXC_PAD_033); +} + +#ifdef CONFIG_CMD_NET +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + struct fec_info_s *info = (struct fec_info_s *)dev->priv; + + __raw_writel(0x00203191, IOMUXC_PAD_000); /* RMII_CLK */ + + if (setclear) { + if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { + __raw_writel(0x00103192, IOMUXC_PAD_045); /*MDC*/ + __raw_writel(0x00103193, IOMUXC_PAD_046); /*MDIO*/ + __raw_writel(0x00103191, IOMUXC_PAD_047); /*RxDV*/ + __raw_writel(0x00103191, IOMUXC_PAD_048); /*RxD1*/ + __raw_writel(0x00103191, IOMUXC_PAD_049); /*RxD0*/ + __raw_writel(0x00103191, IOMUXC_PAD_050); /*RxER*/ + __raw_writel(0x00103192, IOMUXC_PAD_051); /*TxD1*/ + __raw_writel(0x00103192, IOMUXC_PAD_052); /*TxD0*/ + __raw_writel(0x00103192, IOMUXC_PAD_053); /*TxEn*/ + } + if (info->iobase == CONFIG_SYS_FEC1_IOBASE) { + __raw_writel(0x00103192, IOMUXC_PAD_054); /*MDC*/ + __raw_writel(0x00103193, IOMUXC_PAD_055); /*MDIO*/ + __raw_writel(0x00103191, IOMUXC_PAD_056); /*RxDV*/ + __raw_writel(0x00103191, IOMUXC_PAD_057); /*RxD1*/ + __raw_writel(0x00103191, IOMUXC_PAD_058); /*RxD0*/ + __raw_writel(0x00103191, IOMUXC_PAD_059); /*RxER*/ + __raw_writel(0x00103192, IOMUXC_PAD_060); /*TxD1*/ + __raw_writel(0x00103192, IOMUXC_PAD_061); /*TxD0*/ + __raw_writel(0x00103192, IOMUXC_PAD_062); /*TxEn*/ + } + } else { + if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { + __raw_writel(0x00003192, IOMUXC_PAD_045); /*MDC*/ + __raw_writel(0x00003193, IOMUXC_PAD_046); /*MDIO*/ + __raw_writel(0x00003191, IOMUXC_PAD_047); /*RxDV*/ + __raw_writel(0x00003191, IOMUXC_PAD_048); /*RxD1*/ + __raw_writel(0x00003191, IOMUXC_PAD_049); /*RxD0*/ + __raw_writel(0x00003191, IOMUXC_PAD_050); /*RxER*/ + __raw_writel(0x00003192, IOMUXC_PAD_051); /*TxD1*/ + __raw_writel(0x00003192, IOMUXC_PAD_052); /*TxD0*/ + __raw_writel(0x00003192, IOMUXC_PAD_053); /*TxEn*/ + } + if (info->iobase == CONFIG_SYS_FEC1_IOBASE) { + __raw_writel(0x00003192, IOMUXC_PAD_054); /*MDC*/ + __raw_writel(0x00003193, IOMUXC_PAD_055); /*MDIO*/ + __raw_writel(0x00003191, IOMUXC_PAD_056); /*RxDV*/ + __raw_writel(0x00003191, IOMUXC_PAD_057); /*RxD1*/ + __raw_writel(0x00003191, IOMUXC_PAD_058); /*RxD0*/ + __raw_writel(0x00003191, IOMUXC_PAD_059); /*RxER*/ + __raw_writel(0x00003192, IOMUXC_PAD_060); /*TxD1*/ + __raw_writel(0x00003192, IOMUXC_PAD_061); /*TxD0*/ + __raw_writel(0x00003192, IOMUXC_PAD_062); /*TxEn*/ + } + } + + return 0; +} +#endif + +#ifdef CONFIG_QUAD_SPI +void setup_iomux_quadspi(void) +{ + __raw_writel(0x001030C3, IOMUXC_PAD_079); /* SCK */ + __raw_writel(0x001030FF, IOMUXC_PAD_080); /* CS0 */ + __raw_writel(0x001030C3, IOMUXC_PAD_081); /* D3 */ + __raw_writel(0x001030C3, IOMUXC_PAD_082); /* D2 */ + __raw_writel(0x001030C3, IOMUXC_PAD_083); /* D1 */ + __raw_writel(0x001030C3, IOMUXC_PAD_084); /* D0 */ + + __raw_writel(0x001030C3, IOMUXC_PAD_086); /* SCK */ + __raw_writel(0x001030FF, IOMUXC_PAD_087); /* CS0 */ + __raw_writel(0x001030C3, IOMUXC_PAD_088); /* D3 */ + __raw_writel(0x001030C3, IOMUXC_PAD_089); /* D2 */ + __raw_writel(0x001030C3, IOMUXC_PAD_090); /* D1 */ + __raw_writel(0x001030C3, IOMUXC_PAD_091); /* D0 */ +} +#endif + +#ifdef CONFIG_FSL_ESDHC +int board_mmc_getcd(struct mmc *mmc) +{ + int ret; + + __raw_writel(0x005031ef, IOMUXC_PAD_014); /* clk */ + __raw_writel(0x005031ef, IOMUXC_PAD_015); /* cmd */ + __raw_writel(0x005031ef, IOMUXC_PAD_016); /* dat0 */ + __raw_writel(0x005031ef, IOMUXC_PAD_017); /* dat1 */ + __raw_writel(0x005031ef, IOMUXC_PAD_018); /* dat2 */ + __raw_writel(0x005031ef, IOMUXC_PAD_019); /* dat3 */ + + ret = 1; + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + u32 index = 0; + s32 status = 0; + + esdhc_cfg[0].sdhc_clk = 132000000; + esdhc_cfg[1].sdhc_clk = 132000000; + status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]); + return status; +} +#endif + +#ifdef CONFIG_NAND_FSL_NFC +void setup_iomux_nfc(void) +{ + __raw_writel(0x002038df, IOMUXC_PAD_063); + __raw_writel(0x002038df, IOMUXC_PAD_064); + __raw_writel(0x002038df, IOMUXC_PAD_065); + __raw_writel(0x002038df, IOMUXC_PAD_066); + __raw_writel(0x002038df, IOMUXC_PAD_067); + __raw_writel(0x002038df, IOMUXC_PAD_068); + __raw_writel(0x002038df, IOMUXC_PAD_069); + __raw_writel(0x002038df, IOMUXC_PAD_070); + __raw_writel(0x002038df, IOMUXC_PAD_071); + __raw_writel(0x002038df, IOMUXC_PAD_072); + __raw_writel(0x002038df, IOMUXC_PAD_073); + __raw_writel(0x002038df, IOMUXC_PAD_074); + __raw_writel(0x002038df, IOMUXC_PAD_075); + __raw_writel(0x002038df, IOMUXC_PAD_076); + __raw_writel(0x002038df, IOMUXC_PAD_077); + __raw_writel(0x002038df, IOMUXC_PAD_078); + + __raw_writel(0x005038d2, IOMUXC_PAD_094); + __raw_writel(0x005038d2, IOMUXC_PAD_095); + __raw_writel(0x006038d2, IOMUXC_PAD_097); + __raw_writel(0x005038dd, IOMUXC_PAD_099); + __raw_writel(0x006038d2, IOMUXC_PAD_100); + __raw_writel(0x006038d2, IOMUXC_PAD_101); +} +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); +#ifdef CONFIG_NAND_FSL_NFC + setup_iomux_nfc(); +#endif + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + return 0; +} + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_MXC_SPI + setup_iomux_spi(); +#endif + return 0; +} +#endif + +int checkboard(void) +{ + puts("Board: Vybrid\n"); + + return 0; +} diff --git a/board/freescale/vybrid/vybridimage.cfg b/board/freescale/vybrid/vybridimage.cfg new file mode 100644 index 0000000..5da5659 --- /dev/null +++ b/board/freescale/vybrid/vybridimage.cfg @@ -0,0 +1,44 @@ +# +# Copyright 2012-2013 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not write to the Free Software +# Foundation Inc. 51 Franklin Street Fifth Floor Boston, +# MA 02110-1301 USA +# +# Refer docs/README.imxmage for more details about how-to configure +# and create imximage boot image +# +# The syntax is taken as close as possible with the kwbimage + +IMAGE_VERSION 2 + +# Boot Device : one of +# spi, sd (the board has no nand neither onenand) + +BOOT_FROM sd + +# Device Configuration Data (DCD) +# +# Each entry must have the format: +# Addr-type Address Value +# +# where: +# Addr-type register length (1,2 or 4 bytes) +# Address absolute address of the register +# value value to be stored in the register + +# Setting IOMUXC diff --git a/boards.cfg b/boards.cfg index 7725a15..2700a76 100644 --- a/boards.cfg +++ b/boards.cfg @@ -244,6 +244,8 @@ am335x_evm_uart5 arm armv7 am335x ti am335x_evm_usbspl arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,SPL_USBETH_SUPPORT pcm051 arm armv7 pcm051 phytec am33xx pcm051 highbank arm armv7 highbank - highbank +vybrid arm armv7 vybrid freescale vybrid vybrid:VYBRID_CONFIG=board/freescale/vybrid/vybridimage.cfg +vybrid_iram arm armv7 vybrid freescale vybrid vybrid_iram:VYBRID_CONFIG=board/freescale/vybrid/vybridimage.cfg mx51_efikamx arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg mx51_efikasb arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg mx51evk arm armv7 mx51evk freescale mx5 mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg diff --git a/include/configs/vybrid.h b/include/configs/vybrid.h new file mode 100644 index 0000000..d915bd0 --- /dev/null +++ b/include/configs/vybrid.h @@ -0,0 +1,284 @@ +/* + * Copyright 2012-2013 Freescale Semiconductor, Inc. + * + * Configuration settings for the vybrid Board + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + + /* High Level Configuration Options */ + +#define CONFIG_VYBRID + +#define CONFIG_SYS_VYBRID_HCLK 24000000 +#define CONFIG_SYS_VYBRID_CLK32 32768 +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_SYS_IPG + +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_CACHELINE_SIZE 64 + +#include <asm/arch/vybrid-regs.h> + +/* + * Disabled for now due to build problems under Debian and a significant + * increase in the final file size: 144260 vs. 109536 Bytes. + */ + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#undef CONFIG_SETUP_MEMORY_TAGS +#undef CONFIG_INITRD_TAG + +#undef CONFIG_OF_LIBFDT + +#define CONFIG_MACH_TYPE MACH_TYPE_VYBRID_VF6XX +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) + +#define CONFIG_BOARD_LATE_INIT + +/* Hardware drivers */ +#define CONFIG_VYBRID_UART +#define CONFIG_VYBRID_UART_BASE UART0_BASE +#define CONFIG_VYBRID_GPIO + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_SYS_UART_PORT (1) +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/* Command definition */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_BDI /* bdinfo */ +#define CONFIG_CMD_BOOTD +#define CONFIG_CMD_CONSOLE /* coninfo */ +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */ +#define CONFIG_CMD_MISC +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#undef CONFIG_CMD_NFS /* NFS support */ +#define CONFIG_CMD_PING +#undef CONFIG_CMD_NAND +#undef CONFIG_CMD_DATE +#undef CONFIG_CMD_IMI /* iminfo */ +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_LOADB /* loadb */ +#undef CONFIG_CMD_LOADS /* loads */ + +#define CONFIG_SYS_TEXT_BASE 0x3f000800 + +#define CONFIG_MMC +#ifdef CONFIG_MMC +#define CONFIG_SYS_ESDHC1_BASE ESDHC2_BASE_ADDR +#define CONFIG_SYS_ESDHC2_BASE ESDHC2_BASE_ADDR +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_NUM 1 + +#define CONFIG_SYS_FSL_ERRATUM_ESDHC135 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 + +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* + * NAND FLASH + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_MTD_NAND_FSL_NFC_SWECC 1 +#define CONFIG_JFFS2_NAND +#define CONFIG_NAND_FSL_NFC +#define CONFIG_SYS_NAND_BASE 0x400E0000 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE +#define CONFIG_SYS_NAND_SELECT_DEVICE +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ +#endif + +#define CONFIG_QUAD_SPI + +/* Network configuration */ +#define CONFIG_MCFFEC +#ifdef CONFIG_MCFFEC +# define CONFIG_MII 1 +# define CONFIG_MII_INIT 1 +# define CONFIG_SYS_DISCOVER_PHY +# define CONFIG_SYS_RX_ETH_BUFFER 8 +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN + +# define CONFIG_SYS_FEC0_PINMUX 0 +# define CONFIG_SYS_FEC1_PINMUX 0 +# define CONFIG_SYS_FEC0_IOBASE MACNET0_BASE_ADDR +# define CONFIG_SYS_FEC1_IOBASE MACNET1_BASE_ADDR +# define CONFIG_SYS_FEC0_MIIBASE MACNET0_BASE_ADDR +# define CONFIG_SYS_FEC1_MIIBASE MACNET0_BASE_ADDR +# define MCFFEC_TOUT_LOOP 50000 +# undef CONFIG_HAS_ETH1 + +# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 +# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61 +# define CONFIG_ETHPRIME "FEC0" +# define CONFIG_IPADDR 10.81.67.175 +# define CONFIG_NETMASK 255.255.252.0 +# define CONFIG_SERVERIP 10.81.64.153 +# define CONFIG_GATEWAYIP 10.81.67.254 +# define CONFIG_OVERWRITE_ETHADDR_ONCE + +/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CONFIG_SYS_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CONFIG_SYS_DISCOVER_PHY */ +#endif + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ETHPRIME "FEC0" +#define CONFIG_LOADADDR 0x80010000 /* loadaddr env var */ +#define CONFIG_ARP_TIMEOUT 200UL + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT "Vybrid U-Boot > " +#undef CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_MEMTEST_START 0x80010000 +#define CONFIG_SYS_MEMTEST_END 0x87C00000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_HZ 1000 +#undef CONFIG_CMDLINE_EDITING + +#define CONFIG_PRAM 2048 + +/* + * Stack sizes + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) + +#define CONFIG_SYS_SDRAM_BASE (0x80000000) +#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) +#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) + +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* timer */ +#define FTM_BASE_ADDR FTM0_BASE_ADDR +#define CONFIG_TMR_USEPIT + +/* clock/PLL configuration */ +/* uart0-2 */ +#define CONFIG_SYS_CLKCTL_CCGR0 0x000FC000 +/* crc, pit, ftm0/1, a5/m4 wdog */ +#define CONFIG_SYS_CLKCTL_CCGR1 0xF00FC0C0 +/* lptmr, qspi0, iomuxc, gpio */ +#define CONFIG_SYS_CLKCTL_CCGR2 0x0FFF0303 +/* anadig, scscm*/ +#define CONFIG_SYS_CLKCTL_CCGR3 0x00000033 +/* acrc, i2c0/1, wkup, ccm, gpc, src */ +#define CONFIG_SYS_CLKCTL_CCGR4 0x33f0f003 +#define CONFIG_SYS_CLKCTL_CCGR5 0xFFFFFFFF +/* ocotp, snvs, wdog_snvs, ddrmc */ +#define CONFIG_SYS_CLKCTL_CCGR6 0x3003cc00 +/* usb1, sdhc0/1 */ +#define CONFIG_SYS_CLKCTL_CCGR7 0x0000033c +/* qspi1 */ +#define CONFIG_SYS_CLKCTL_CCGR8 0x00000300 +/* enet0/1 */ +#define CONFIG_SYS_CLKCTL_CCGR9 0x0000000f +/* nfc */ +#define CONFIG_SYS_CLKCTL_CCGR10 0x00000003 +/* caam */ +#define CONFIG_SYS_CLKCTL_CCGR11 0x00000003 + +#define CONFIG_SYS_CLKCTRL_CCR 0x00010005 +#define CONFIG_SYS_CLKCTRL_CCSR 0x0003FF64 +#define CONFIG_SYS_CLKCTRL_CACRR 0x00000810 +#define CONFIG_SYS_CLKCTRL_CSCMR1 0x03CA0000 +#define CONFIG_SYS_CLKCTRL_CSCDR1 0x01000000 +#define CONFIG_SYS_CLKCTRL_CSCDR2 0x30114240 +#define CONFIG_SYS_CLKCTRL_CSCDR3 0x00003F1F +#define CONFIG_SYS_CLKCTRL_CSCMR2 0x00000000 +#define CONFIG_SYS_CLKCTRL_CSCDR4 0x00000000 +#define CONFIG_SYS_CLKCTRL_CLPCR 0x00000078 + +#define CONFIG_SYS_ANADIG_USB1_CTRL 0x00012000 +#define CONFIG_SYS_ANADIG_USB2_CTRL 0x00012000 +#define CONFIG_SYS_ANADIG_528_CTRL 0x00002001 +#define CONFIG_SYS_ANADIG_528_SS 0x00000000 +#define CONFIG_SYS_ANADIG_528_NUM 0x00000000 +#define CONFIG_SYS_ANADIG_528_DENOM 0x00000012 +#define CONFIG_SYS_ANADIG_VID_CTRL 0x00011028 +#define CONFIG_SYS_ANADIG_VID_NUM 0x00000000 +#define CONFIG_SYS_ANADIG_VID_DENOM 0x00000012 +#define CONFIG_SYS_ANADIG_ENET_CTRL 0x00011001 +#define CONFIG_SYS_ANADIG_PFD_USB1 0x1B1D1A1C +#define CONFIG_SYS_ANADIG_PFD_528 0x171C1813 +#define CONFIG_SYS_ANADIG_USB1_MISC 0x00000002 +#define CONFIG_SYS_ANADIG_USB2_VBUS 0x00100004 +#define CONFIG_SYS_ANADIG_USB2_CHRG 0x00000000 +#define CONFIG_SYS_ANADIG_USB2_MISC 0x00000002 +#define CONFIG_SYS_ANADIG_SYS_CTRL 0x00002001 +#define CONFIG_SYS_ANADIG_SYS_SS 0x00000000 +#define CONFIG_SYS_ANADIG_SYS_NUM 0x00000000 +#define CONFIG_SYS_ANADIG_SYS_DENOM 0x00000012 +#define CONFIG_SYS_ANADIG_SYS_PFD_528 0x00000000 +#define CONFIG_SYS_ANADIG_SYS_PLL_LOCK 0x00000000 + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ENV_OFFSET (12 * 64 * 1024) +#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#endif diff --git a/include/configs/vybrid_iram.h b/include/configs/vybrid_iram.h new file mode 100644 index 0000000..f88050e --- /dev/null +++ b/include/configs/vybrid_iram.h @@ -0,0 +1,284 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Configuration settings for the vybrid Board + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ + +#define CONFIG_VYBRID + +#define CONFIG_SYS_VYBRID_HCLK 24000000 +#define CONFIG_SYS_VYBRID_CLK32 32768 +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_SYS_IPG + +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_CACHELINE_SIZE 64 + +#define CONFIG_SYS_UBOOT_IN_GPURAM + +#include <asm/arch/vybrid-regs.h> + +/* + * Disabled for now due to build problems under Debian and a significant + * increase in the final file size: 144260 vs. 109536 Bytes. + */ + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#undef CONFIG_SETUP_MEMORY_TAGS +#undef CONFIG_INITRD_TAG + +#undef CONFIG_OF_LIBFDT + +#define CONFIG_MACH_TYPE MACH_TYPE_VYBRID_VF6XX + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 << 10) + +#define CONFIG_BOARD_LATE_INIT + +/* Hardware drivers */ +#define CONFIG_VYBRID_UART +#define CONFIG_VYBRID_UART_BASE UART0_BASE +#define CONFIG_VYBRID_GPIO + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_SYS_UART_PORT (1) +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/* Command definition */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_BDI /* bdinfo */ +#define CONFIG_CMD_BOOTD +#define CONFIG_CMD_CONSOLE /* coninfo */ +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */ +#define CONFIG_CMD_MISC +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#undef CONFIG_CMD_NFS /* NFS support */ +#define CONFIG_CMD_PING +#undef CONFIG_CMD_DATE +#undef CONFIG_CMD_IMI /* iminfo */ +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_LOADB /* loadb */ +#undef CONFIG_CMD_LOADS /* loads */ + +#define CONFIG_SYS_TEXT_BASE 0x3f000800 + +#define CONFIG_MMC +#ifdef CONFIG_MMC +#define CONFIG_SYS_ESDHC1_BASE ESDHC2_BASE_ADDR +#define CONFIG_SYS_ESDHC2_BASE ESDHC2_BASE_ADDR +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_NUM 1 + +#define CONFIG_SYS_FSL_ERRATUM_ESDHC135 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 + +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* + * NAND FLASH + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_JFFS2_NAND +#define CONFIG_NAND_FSL_NFC +#define CONFIG_SYS_NAND_BASE 0x400E0000 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE +#define CONFIG_SYS_NAND_SELECT_DEVICE +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ +#endif + +#define CONFIG_QUAD_SPI + +/* Network configuration */ +#define CONFIG_MCFFEC +#ifdef CONFIG_MCFFEC +# define CONFIG_MII 1 +# define CONFIG_MII_INIT 1 +# define CONFIG_SYS_DISCOVER_PHY +# define CONFIG_SYS_RX_ETH_BUFFER 8 +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN + +# define CONFIG_SYS_FEC0_PINMUX 0 +# define CONFIG_SYS_FEC1_PINMUX 0 +# define CONFIG_SYS_FEC0_IOBASE MACNET0_BASE_ADDR +# define CONFIG_SYS_FEC1_IOBASE MACNET1_BASE_ADDR +# define CONFIG_SYS_FEC0_MIIBASE MACNET0_BASE_ADDR +# define CONFIG_SYS_FEC1_MIIBASE MACNET0_BASE_ADDR +# define MCFFEC_TOUT_LOOP 50000 +# undef CONFIG_HAS_ETH1 + +# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 +# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61 +# define CONFIG_ETHPRIME "FEC0" +# define CONFIG_IPADDR 10.81.67.175 +# define CONFIG_NETMASK 255.255.252.0 +# define CONFIG_SERVERIP 10.81.64.153 +# define CONFIG_GATEWAYIP 10.81.67.254 +# define CONFIG_OVERWRITE_ETHADDR_ONCE + +/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CONFIG_SYS_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CONFIG_SYS_DISCOVER_PHY */ +#endif + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ETHPRIME "FEC0" +#define CONFIG_LOADADDR 0x3f400000 /* loadaddr env var */ +#define CONFIG_ARP_TIMEOUT 200UL + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT "Vybrid U-Boot > " +#undef CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_MEMTEST_START 0x3f400000 +#define CONFIG_SYS_MEMTEST_END 0x10000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_HZ 1000 +#undef CONFIG_CMDLINE_EDITING + +/* + * Stack sizes + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) + +#define CONFIG_SYS_SDRAM_BASE (0x3f400000) +#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) +#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) + +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* timer */ +#define FTM_BASE_ADDR FTM0_BASE_ADDR +#define CONFIG_TMR_USEPIT + +/* clock/PLL configuration */ +/* uart0-2 */ +#define CONFIG_SYS_CLKCTL_CCGR0 0x000FC000 +/* crc, pit, ftm0/1, a5/m4 wdog */ +#define CONFIG_SYS_CLKCTL_CCGR1 0xF00FC0C0 +/* lptmr, qspi0, iomuxc, gpio */ +#define CONFIG_SYS_CLKCTL_CCGR2 0x0FFF0303 +/* anadig, scscm*/ +#define CONFIG_SYS_CLKCTL_CCGR3 0x00000033 +/* acrc, i2c0/1, wkup, ccm, gpc, src */ +#define CONFIG_SYS_CLKCTL_CCGR4 0x33f0f003 +#define CONFIG_SYS_CLKCTL_CCGR5 0xFFFFFFFF +/* ocotp, snvs, wdog_snvs, ddrmc */ +#define CONFIG_SYS_CLKCTL_CCGR6 0x3003cc00 +/* usb1, sdhc0/1 */ +#define CONFIG_SYS_CLKCTL_CCGR7 0x0000033c +/* qspi1 */ +#define CONFIG_SYS_CLKCTL_CCGR8 0x00000300 +/* enet0/1 */ +#define CONFIG_SYS_CLKCTL_CCGR9 0x0000000f +/* nfc */ +#define CONFIG_SYS_CLKCTL_CCGR10 0x00000003 +/* caam */ +#define CONFIG_SYS_CLKCTL_CCGR11 0x00000003 + +#define CONFIG_SYS_CLKCTRL_CCR 0x00010005 +#define CONFIG_SYS_CLKCTRL_CCSR 0x0003FF64 +#define CONFIG_SYS_CLKCTRL_CACRR 0x00000810 +#define CONFIG_SYS_CLKCTRL_CSCMR1 0x03CA0000 +#define CONFIG_SYS_CLKCTRL_CSCDR1 0x01000000 +#define CONFIG_SYS_CLKCTRL_CSCDR2 0x30114240 +#define CONFIG_SYS_CLKCTRL_CSCDR3 0x00003F1F +#define CONFIG_SYS_CLKCTRL_CSCMR2 0x00000000 +#define CONFIG_SYS_CLKCTRL_CSCDR4 0x00000000 +#define CONFIG_SYS_CLKCTRL_CLPCR 0x00000078 + +#define CONFIG_SYS_ANADIG_USB1_CTRL 0x00012000 +#define CONFIG_SYS_ANADIG_USB2_CTRL 0x00012000 +#define CONFIG_SYS_ANADIG_528_CTRL 0x00002001 +#define CONFIG_SYS_ANADIG_528_SS 0x00000000 +#define CONFIG_SYS_ANADIG_528_NUM 0x00000000 +#define CONFIG_SYS_ANADIG_528_DENOM 0x00000012 +#define CONFIG_SYS_ANADIG_VID_CTRL 0x00011028 +#define CONFIG_SYS_ANADIG_VID_NUM 0x00000000 +#define CONFIG_SYS_ANADIG_VID_DENOM 0x00000012 +#define CONFIG_SYS_ANADIG_ENET_CTRL 0x00011001 +#define CONFIG_SYS_ANADIG_PFD_USB1 0x1B1D1A1C +#define CONFIG_SYS_ANADIG_PFD_528 0x171C1813 +#define CONFIG_SYS_ANADIG_USB1_MISC 0x00000002 +#define CONFIG_SYS_ANADIG_USB2_VBUS 0x00100004 +#define CONFIG_SYS_ANADIG_USB2_CHRG 0x00000000 +#define CONFIG_SYS_ANADIG_USB2_MISC 0x00000002 +#define CONFIG_SYS_ANADIG_SYS_CTRL 0x00002001 +#define CONFIG_SYS_ANADIG_SYS_SS 0x00000000 +#define CONFIG_SYS_ANADIG_SYS_NUM 0x00000000 +#define CONFIG_SYS_ANADIG_SYS_DENOM 0x00000012 +#define CONFIG_SYS_ANADIG_SYS_PFD_528 0x00000000 +#define CONFIG_SYS_ANADIG_SYS_PLL_LOCK 0x00000000 + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ENV_OFFSET (6 * 64 * 1024) +#define CONFIG_ENV_SIZE (8 * 1024) +#undef CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#endif