Patchwork mtd: fsl_ifc_nand: set NAND_NO_SUBPAGE_WRITE

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Submitter Scott Wood
Date April 10, 2013, 10:34 p.m.
Message ID <20130410223437.GA26900@home.buserror.net>
Download mbox | patch
Permalink /patch/235512/
State New
Headers show

Comments

Scott Wood - April 10, 2013, 10:34 p.m.
This controller only does ECC on full-page accesses, even though the
ECC consists of multiple steps.  fsl_elbc_nand can get away with this
because the ECC of an all-0xff region will be all-0xff, but this is not
true with the ECC algorithms used by IFC.

Signed-off-by: Scott Wood <scottwood@freescale.com>
---
 drivers/mtd/nand/fsl_ifc_nand.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
Artem Bityutskiy - May 10, 2013, 2:48 p.m.
On Wed, 2013-04-10 at 17:34 -0500, Scott Wood wrote:
> This controller only does ECC on full-page accesses, even though the
> ECC consists of multiple steps.  fsl_elbc_nand can get away with this
> because the ECC of an all-0xff region will be all-0xff, but this is not
> true with the ECC algorithms used by IFC.
> 
> Signed-off-by: Scott Wood <scottwood@freescale.com>

Pushed to l2-mtd.git, thanks!

Patch

diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index f1f7f12..4e1fc4d 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -823,7 +823,7 @@  static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
 
 	/* set up nand options */
 	chip->bbt_options = NAND_BBT_USE_FLASH;
-
+	chip->options = NAND_NO_SUBPAGE_WRITE;
 
 	if (ioread32be(&ifc->cspr_cs[priv->bank].cspr) & CSPR_PORT_SIZE_16) {
 		chip->read_byte = fsl_ifc_read_byte16;