Patchwork [v2,3/3] clk: sunxi: Unify oscillator clock

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Submitter Mike Turquette
Date April 10, 2013, 10:02 p.m.
Message ID <1365631378-16103-4-git-send-email-mturquette@linaro.org>
Download mbox | patch
Permalink /patch/235495/
State New
Headers show

Comments

Mike Turquette - April 10, 2013, 10:02 p.m.
From: Emilio López <emilio@elopez.com.ar>

This commit uses the new fixed-rate support on the composite clock to
unify osc24M_fixed and osc24M clocks, so it matches the actual hardware.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
[mturquette@linaro.org: replace clk_register_gatable_osc with a call to
clk_register_composite]
---
Emilio,

I haven't been able to test these changes at run-time.  Can you see if
they are valid for solving your issue on sunxi?

 drivers/clk/sunxi/clk-sunxi.c |   33 ++++++++++++++++++++++++++-------
 1 file changed, 26 insertions(+), 7 deletions(-)
Emilio López - April 11, 2013, 12:07 a.m.
Hi Mike,

El 10/04/13 19:02, Mike Turquette escribió:
> From: Emilio López <emilio@elopez.com.ar>
> 
> This commit uses the new fixed-rate support on the composite clock to
> unify osc24M_fixed and osc24M clocks, so it matches the actual hardware.
> 
> Signed-off-by: Emilio López <emilio@elopez.com.ar>
> Signed-off-by: Mike Turquette <mturquette@linaro.org>
> [mturquette@linaro.org: replace clk_register_gatable_osc with a call to
> clk_register_composite]
> ---
> Emilio,
> 
> I haven't been able to test these changes at run-time.  Can you see if
> they are valid for solving your issue on sunxi?

I tested the three patches you sent + 3/3 from the original series which
is the DT part.

$ git log --oneline -n 4
b63f51e ARM: sunxi: unify osc24M_fixed and osc24M
7f86473 clk: sunxi: Unify oscillator clock
78c8aaf clk: composite: allow fixed rates & fixed dividers
2d52a44 clk: composite: rename 'div' references to 'rate'

It seems to be working fine as far as I can tell, so

Tested-by: Emilio López <emilio@elopez.com.ar>

Thanks,

Emilio
Mike Turquette - April 12, 2013, 6:40 p.m.
Quoting Emilio López (2013-04-10 17:07:21)
> Hi Mike,
> 
> El 10/04/13 19:02, Mike Turquette escribió:
> > From: Emilio López <emilio@elopez.com.ar>
> > 
> > This commit uses the new fixed-rate support on the composite clock to
> > unify osc24M_fixed and osc24M clocks, so it matches the actual hardware.
> > 
> > Signed-off-by: Emilio López <emilio@elopez.com.ar>
> > Signed-off-by: Mike Turquette <mturquette@linaro.org>
> > [mturquette@linaro.org: replace clk_register_gatable_osc with a call to
> > clk_register_composite]
> > ---
> > Emilio,
> > 
> > I haven't been able to test these changes at run-time.  Can you see if
> > they are valid for solving your issue on sunxi?
> 
> I tested the three patches you sent + 3/3 from the original series which
> is the DT part.
> 
> $ git log --oneline -n 4
> b63f51e ARM: sunxi: unify osc24M_fixed and osc24M
> 7f86473 clk: sunxi: Unify oscillator clock
> 78c8aaf clk: composite: allow fixed rates & fixed dividers
> 2d52a44 clk: composite: rename 'div' references to 'rate'
> 
> It seems to be working fine as far as I can tell, so
> 
> Tested-by: Emilio López <emilio@elopez.com.ar>
> 

I've applied all three patches to clk-next.  I assume the DT patch will
go through Maxime's tree.

Regards,
Mike

> Thanks,
> 
> Emilio

Patch

diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 0bb0eb4..8492ad1 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -33,16 +33,36 @@  static DEFINE_SPINLOCK(clk_lock);
 static void __init sunxi_osc_clk_setup(struct device_node *node)
 {
 	struct clk *clk;
+	struct clk_fixed_rate *fixed;
+	struct clk_gate *gate;
 	const char *clk_name = node->name;
-	const char *parent;
-	void *reg;
+	u32 rate;
 
-	reg = of_iomap(node, 0);
+	/* allocate fixed-rate and gate clock structs */
+	fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL);
+	if (!fixed)
+		return;
+	gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
+	if (!gate) {
+		kfree(fixed);
+		return;
+	}
 
-	parent = of_clk_get_parent_name(node, 0);
+	if (of_property_read_u32(node, "clock-frequency", &rate))
+		return;
+
+	/* set up gate and fixed rate properties */
+	gate->reg = of_iomap(node, 0);
+	gate->bit_idx = SUNXI_OSC24M_GATE;
+	gate->lock = &clk_lock;
+	fixed->fixed_rate = rate;
 
-	clk = clk_register_gate(NULL, clk_name, parent, 0, reg,
-				SUNXI_OSC24M_GATE, 0, &clk_lock);
+	clk = clk_register_composite(NULL, clk_name,
+			NULL, 0,
+			NULL, NULL,
+			&fixed->hw, &clk_fixed_rate_ops,
+			&gate->hw, &clk_gate_ops,
+			CLK_IS_ROOT);
 
 	if (clk) {
 		of_clk_add_provider(node, of_clk_src_simple_get, clk);
@@ -380,7 +400,6 @@  static void __init sunxi_gates_clk_setup(struct device_node *node,
 
 /* Matches for of_clk_init */
 static const __initconst struct of_device_id clk_match[] = {
-	{.compatible = "fixed-clock", .data = of_fixed_clk_setup,},
 	{.compatible = "allwinner,sun4i-osc-clk", .data = sunxi_osc_clk_setup,},
 	{}
 };