From patchwork Wed Apr 10 12:07:50 2013
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Subject: [U-Boot,1/4] driver:usb:s3c_udc: add support for Exynos4x12
X-Patchwork-Submitter: Piotr Wilczek
X-Patchwork-Id: 235378
X-Patchwork-Delegate: promsoft@gmail.com
Message-Id: <1365595673-23272-2-git-send-email-p.wilczek@samsung.com>
To: u-boot@lists.denx.de
Cc: Piotr Wilczek ,
Kyungmin Park
Date: Wed, 10 Apr 2013 14:07:50 +0200
From: Piotr Wilczek
List-Id: U-Boot discussion
This patch add new defines for usb phy for Exynos4x12.
Signed-off-by: Piotr Wilczek
Signed-off-by: Kyungmin Park
CC: Minkyu Kang
---
drivers/usb/gadget/regs-otg.h | 5 +++++
drivers/usb/gadget/s3c_udc_otg.c | 9 +++++++--
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/gadget/regs-otg.h b/drivers/usb/gadget/regs-otg.h
index 3737e45..df7cda6 100644
--- a/drivers/usb/gadget/regs-otg.h
+++ b/drivers/usb/gadget/regs-otg.h
@@ -229,6 +229,11 @@ struct s3c_usbotg_reg {
#define CLK_SEL_12MHZ (0x2 << 0)
#define CLK_SEL_48MHZ (0x0 << 0)
+#define EXYNOS4X12_ID_PULLUP0 (0x01 << 3)
+#define EXYNOS4X12_COMMON_ON_N0 (0x01 << 4)
+#define EXYNOS4X12_CLK_SEL_12MHZ (0x02 << 0)
+#define EXYNOS4X12_CLK_SEL_24MHZ (0x05 << 0)
+
/* Device Configuration Register DCFG */
#define DEV_SPEED_HIGH_SPEED_20 (0x0 << 0)
#define DEV_SPEED_FULL_SPEED_20 (0x1 << 0)
diff --git a/drivers/usb/gadget/s3c_udc_otg.c b/drivers/usb/gadget/s3c_udc_otg.c
index f9d24e3..fb72662 100644
--- a/drivers/usb/gadget/s3c_udc_otg.c
+++ b/drivers/usb/gadget/s3c_udc_otg.c
@@ -180,8 +180,13 @@ void otg_phy_init(struct s3c_udc *dev)
writel((readl(&phy->phypwr) &~(OTG_DISABLE_0 | ANALOG_PWRDOWN)
&~FORCE_SUSPEND_0), &phy->phypwr);
- writel((readl(&phy->phyclk) &~(ID_PULLUP0 | COMMON_ON_N0)) |
- CLK_SEL_24MHZ, &phy->phyclk); /* PLL 24Mhz */
+ if (proid_is_exynos4412())
+ writel((readl(&phy->phyclk) &~(EXYNOS4X12_ID_PULLUP0 |
+ EXYNOS4X12_COMMON_ON_N0)) | EXYNOS4X12_CLK_SEL_24MHZ,
+ &phy->phyclk); /* PLL 24Mhz */
+ else
+ writel((readl(&phy->phyclk) &~(ID_PULLUP0 | COMMON_ON_N0)) |
+ CLK_SEL_24MHZ, &phy->phyclk); /* PLL 24Mhz */
writel((readl(&phy->rstcon) &~(LINK_SW_RST | PHYLNK_SW_RST))
| PHY_SW_RST0, &phy->rstcon);