From patchwork Wed Apr 10 10:35:06 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Hurugalawadi, Naveen" X-Patchwork-Id: 235354 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "localhost", Issuer "www.qmailtoaster.com" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 91C652C00C1 for ; Wed, 10 Apr 2013 20:35:30 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:content-type:mime-version; q=dns; s= default; b=HVBTOZtdaKmLFK5Vd+UO5XYofJJQ4Ff28oKH+m9I1A4A04Al8Lz5a uCte+xEQCNH227oyZsZRxTURpC2r9afyQSSFONqDt9QqxDx+EUXedubgpyBMuVAz /Sgrrwb8srGyvCkhSYU7DgVuLHI5y2PAknfzzDWpEd7PDu2mhuM+Bg= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:content-type:mime-version; s= default; bh=JVfNLRdZon8CuajqwWUAyFr5NK8=; b=OgUutP5TnpnEzR7LJ+bo DcxoS6/X7r9FFD08IwDjFNfTbJEo191mwfLv/pYHuSYEopVtC3sBY1u7SpFPH8XK hgzbJIfFFCWZi7CO5jEqFEFiYuSxvay52wGAmKqDnQlMMzME28nNXDMfpR850h0w 4fjO/O8cZxauJGu0mo8A9S8= Received: (qmail 2948 invoked by alias); 10 Apr 2013 10:35:24 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 2937 invoked by uid 89); 10 Apr 2013 10:35:23 -0000 X-Spam-SWARE-Status: No, score=-4.1 required=5.0 tests=AWL, BAYES_00, KHOP_RCVD_UNTRUST, RCVD_IN_DNSWL_LOW, RCVD_IN_HOSTKARMA_W, RCVD_IN_HOSTKARMA_WL autolearn=ham version=3.3.1 Received: from va3ehsobe005.messaging.microsoft.com (HELO va3outboundpool.messaging.microsoft.com) (216.32.180.31) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Wed, 10 Apr 2013 10:35:16 +0000 Received: from mail164-va3-R.bigfish.com (10.7.14.251) by VA3EHSOBE010.bigfish.com (10.7.40.12) with Microsoft SMTP Server id 14.1.225.23; Wed, 10 Apr 2013 10:35:14 +0000 Received: from mail164-va3 (localhost [127.0.0.1]) by mail164-va3-R.bigfish.com (Postfix) with ESMTP id 69E894E0116 for ; Wed, 10 Apr 2013 10:35:14 +0000 (UTC) X-Forefront-Antispam-Report: CIP:157.56.236.133; KIP:(null); UIP:(null); IPV:NLI; H:BY2PRD0710HT005.namprd07.prod.outlook.com; RD:none; EFVD:NLI X-SpamScore: -2 X-BigFish: PS-2(zz936eIc85fh4015Izz1f42h1fc6h1ee6h1de0h1fdah1202h1e76h1d1ah1d2ahzz8275bhz2dh2a8h668h839hd25hf0ah1288h12a5h12bdh137ah1441h1504h1537h153bh15d0h162dh1631h1758h18e1h1946h19b5h19ceh1ad9h1b0ah1bceh34h1155h) Received: from mail164-va3 (localhost.localdomain [127.0.0.1]) by mail164-va3 (MessageSwitch) id 1365590111857519_9414; Wed, 10 Apr 2013 10:35:11 +0000 (UTC) Received: from VA3EHSMHS013.bigfish.com (unknown [10.7.14.254]) by mail164-va3.bigfish.com (Postfix) with ESMTP id C398B40004E for ; Wed, 10 Apr 2013 10:35:11 +0000 (UTC) Received: from BY2PRD0710HT005.namprd07.prod.outlook.com (157.56.236.133) by VA3EHSMHS013.bigfish.com (10.7.99.23) with Microsoft SMTP Server (TLS) id 14.1.225.23; Wed, 10 Apr 2013 10:35:07 +0000 Received: from BY2PRD0710MB364.namprd07.prod.outlook.com ([169.254.3.244]) by BY2PRD0710HT005.namprd07.prod.outlook.com ([10.255.86.40]) with mapi id 14.16.0287.008; Wed, 10 Apr 2013 10:35:06 +0000 From: "Hurugalawadi, Naveen" To: "gcc-patches@gcc.gnu.org" Subject: [PATCH, AArch64] Compare Negative instruction in shift and extend mode Date: Wed, 10 Apr 2013 10:35:06 +0000 Message-ID: MIME-Version: 1.0 X-OriginatorOrg: caviumnetworks.com X-Virus-Found: No Hi, Please find attached the patch that implements compare negative instruction with shift and extend mode for aarch64 target. Testcase have been added for compare and compare negative instruction. Please review the same and let me know if there should be any modifications in the patch. Build and tested on aarch64-thunder-elf (using Cavium's internal simulator). No new regressions. Thanks, Naveen gcc/ 2013-04-10 Naveen H.S * config/aarch64/aarch64.c (aarch64_select_cc_mode): Use NEG code in CC_SWP mode. * config/aarch64/aarch64.md (*cmn_swp__reg): New pattern. (*cmn_swp__reg): New pattern. gcc/testsuite/ 2013-04-10 Naveen H.S * gcc.target/aarch64/cmn-1.c: New. * gcc.target/aarch64/cmp.c: New. --- gcc/config/aarch64/aarch64.c 2013-04-09 11:58:48.650789435 +0530 +++ gcc/config/aarch64/aarch64.c 2013-04-10 13:20:12.625311883 +0530 @@ -3094,7 +3094,8 @@ aarch64_select_cc_mode (RTX_CODE code, r the comparison will have to be swapped when we emit the assembly code. */ if ((GET_MODE (x) == SImode || GET_MODE (x) == DImode) - && (GET_CODE (y) == REG || GET_CODE (y) == SUBREG) + && (GET_CODE (y) == REG || GET_CODE (y) == SUBREG + || GET_CODE (y) == NEG) && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND)) --- gcc/config/aarch64/aarch64.md 2013-04-09 11:58:48.646789435 +0530 +++ gcc/config/aarch64/aarch64.md 2013-04-10 12:31:40.393317692 +0530 @@ -2190,7 +2190,28 @@ (set_attr "mode" "")] ) +(define_insn "*cmn_swp__reg" + [(set (reg:CC_SWP CC_REGNUM) + (compare:CC_SWP (ASHIFT:GPI + (match_operand:GPI 0 "register_operand" "r") + (match_operand:QI 1 "aarch64_shift_imm_" "n")) + (neg:GPI (match_operand:GPI 2 "aarch64_reg_or_zero" "rZ"))))] + "" + "cmn\\t%2, %0, %1" + [(set_attr "v8type" "alus_shift") + (set_attr "mode" "")] +) +(define_insn "*cmn_swp__reg" + [(set (reg:CC_SWP CC_REGNUM) + (compare:CC_SWP (ANY_EXTEND:GPI + (match_operand:ALLX 0 "register_operand" "r")) + (neg:GPI (match_operand:GPI 1 "register_operand" "r"))))] + "" + "cmn\\t%1, %0, xt" + [(set_attr "v8type" "alus_ext") + (set_attr "mode" "")] +) ;; ------------------------------------------------------------------- ;; Store-flag and conditional select insns ;; ------------------------------------------------------------------- --- gcc/testsuite/gcc.target/aarch64/cmn-1.c 1970-01-01 05:30:00.000000000 +0530 +++ gcc/testsuite/gcc.target/aarch64/cmn-1.c 2013-04-10 12:27:17.845318216 +0530 @@ -0,0 +1,134 @@ +/* { dg-do run } */ +/* { dg-options "-O2 --save-temps" } */ + +extern void abort (void); + +int +cmn_si_test1 (int a, int b, int c) +{ + /* { dg-final { scan-assembler "cmn\tw\[0-9\]+, w\[0-9\]+" } } */ + if (a + b) + return a + c; + else + return a + b + c; +} + +int +cmn_si_test2 (int a, int b, int c) +{ + /* { dg-final { scan-assembler "cmn\tw\[0-9\]+, w\[0-9\]+, asr 3" } } */ + if ((a >> 3) + b) + return a + c; + else + return a + b + c; +} + +int +cmn_si_test3 (char a, int b, int c) +{ + /* { dg-final { scan-assembler "cmn\tw\[0-9\]+, w\[0-9\]+, uxtb" } } */ + if (a > -b) + return a + c; + else + return a + b + c; +} + +typedef long long s64; + +s64 +cmn_di_test1 (s64 a, s64 b, s64 c) +{ + /* { dg-final { scan-assembler "cmn\tx\[0-9\]+, x\[0-9\]+" } } */ + if (a + b) + return a + c; + else + return a + b + c; +} + +s64 +cmn_di_test2 (s64 a, s64 b, s64 c) +{ + /* { dg-final { scan-assembler "cmn\tx\[0-9\]+, x\[0-9\]+, asr 3" } } */ + if ((a >> 3) + b) + return a + c; + else + return a + b + c; +} + +s64 +cmn_di_test3 (int a, s64 b, s64 c) +{ + /* { dg-final { scan-assembler "cmn\tx\[0-9\]+, x\[0-9\]+, sxtw" } } */ + if (a > -b) + return a + c; + else + return a + b + c; +} + +int main () +{ + int x; + s64 y; + + x = cmn_si_test1 (2, 12, 5); + if (x != 7) + abort (); + + x = cmn_si_test1 (1, 2, 32); + if (x != 33) + abort (); + + x = cmn_si_test2 (7, 5, 15); + if (x != 22) + abort (); + + x = cmn_si_test2 (12, 1, 3); + if (x != 15) + abort (); + + x = cmn_si_test3 (13, 14, 5); + if (x != 18) + abort (); + + x = cmn_si_test3 (15, 21, 2); + if (x != 17) + abort (); + + y = cmn_di_test1 (0x20202020ll, + 0x65161611ll, + 0x42434243ll); + if (y != 0x62636263ll) + abort (); + + y = cmn_di_test1 (0x1010101010101ll, + 0x123456789abcdll, + 0x5555555555555ll); + if (y != 0x6565656565656ll) + abort (); + + y = cmn_di_test2 (0x31313131ll, + 0x35466561ll, + 0x42434243ll); + if (y != 0x73747374ll) + abort (); + + y = cmn_di_test2 (0x101010101ll, + 0x123456789ll, + 0x555555555ll); + if (y != 0x656565656ll) + abort (); + + y = cmn_di_test3 (0x62523781ll, + 0x64234978ll, + 0x12345123ll); + if (y != 0x748688a4ll) + abort (); + + y = cmn_di_test3 (0x76352626ll, + 0x10101010ll, + 0x21212121ll); + if (y != 0x97564747ll) + abort (); + + return 0; +} --- gcc/testsuite/gcc.target/aarch64/cmp.c 1970-01-01 05:30:00.000000000 +0530 +++ gcc/testsuite/gcc.target/aarch64/cmp.c 2013-04-10 12:28:12.897318106 +0530 @@ -0,0 +1,134 @@ +/* { dg-do run } */ +/* { dg-options "-O2 --save-temps" } */ + +extern void abort (void); + +int +cmp_si_test1 (int a, int b, int c) +{ + /* { dg-final { scan-assembler "cmp\tw\[0-9\]+, w\[0-9\]+" } } */ + if (a > b) + return a + c; + else + return a + b + c; +} + +int +cmp_si_test2 (int a, int b, int c) +{ + /* { dg-final { scan-assembler "cmp\tw\[0-9\]+, w\[0-9\]+, asr 3" } } */ + if ((a >> 3) > b) + return a + c; + else + return a + b + c; +} + +int +cmp_si_test3 (int a, long b, int c) +{ + /* { dg-final { scan-assembler "cmp\tx\[0-9\]+, x\[0-9\]+, sxtw" } } */ + if (a > b) + return a + c; + else + return a + b + c; +} + +typedef long long s64; + +s64 +cmp_di_test1 (s64 a, s64 b, s64 c) +{ + /* { dg-final { scan-assembler "cmp\tx\[0-9\]+, x\[0-9\]+" } } */ + if (a > b) + return a + c; + else + return a + b + c; +} + +s64 +cmp_di_test2 (s64 a, s64 b, s64 c) +{ + /* { dg-final { scan-assembler "cmp\tx\[0-9\]+, x\[0-9\]+, asr 3" } } */ + if ((a >> 3) > b) + return a + c; + else + return a + b + c; +} + +int +cmp_di_test3 (int a, s64 b, s64 c) +{ + /* { dg-final { scan-assembler "cmp\tx\[0-9\]+, x\[0-9\]+, sxtw" } } */ + if (a > b) + return a + c; + else + return a + b + c; +} + +int main () +{ + int x; + s64 y; + + x = cmp_si_test1 (2, 12, 5); + if (x != 19) + abort (); + + x = cmp_si_test1 (1, 2, 32); + if (x != 35) + abort (); + + x = cmp_si_test2 (7, 5, 15); + if (x != 27) + abort (); + + x = cmp_si_test2 (12, 1, 3); + if (x != 16) + abort (); + + x = cmp_si_test3 (13, 14, 5); + if (x != 32) + abort (); + + x = cmp_si_test3 (15, 21, 2); + if (x != 38) + abort (); + + y = cmp_di_test1 (0x20202020ll, + 0x65161611ll, + 0x42434243ll); + if (y != 0xc7797874ll) + abort (); + + y = cmp_di_test1 (0x1010101010101ll, + 0x123456789abcdll, + 0x5555555555555ll); + if (y != 0x7799bbde00223ll) + abort (); + + y = cmp_di_test2 (0x31313131ll, + 0x35466561ll, + 0x42434243ll); + if (y != 0xa8bad8d5ll) + abort (); + + y = cmp_di_test2 (0x101010101ll, + 0x123456789ll, + 0x555555555ll); + if (y != 0x7799bbddfll) + abort (); + + y = cmp_di_test3 (0x62523781ll, + 0x64234978ll, + 0x12345123ll); + if (y != 0xffffffffd8a9d21cll) + abort (); + + y = cmp_di_test3 (0x76352626ll, + 0x10101010ll, + 0x21212121ll); + if (y != 0xffffffff97564747ll) + abort (); + + return 0; +}