From patchwork Wed Apr 10 07:06:09 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Roese X-Patchwork-Id: 235309 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 349302C00C6 for ; Wed, 10 Apr 2013 17:09:45 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 357854A026; Wed, 10 Apr 2013 09:09:32 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id UhaOaUwt2WTq; Wed, 10 Apr 2013 09:09:31 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 324244A03F; Wed, 10 Apr 2013 09:08:16 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0A5724A020 for ; Wed, 10 Apr 2013 09:07:49 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id HTBI-uTjvWLQ for ; Wed, 10 Apr 2013 09:07:32 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mo-p05-ob.rzone.de (mo-p05-ob.rzone.de [81.169.146.180]) by theia.denx.de (Postfix) with ESMTP id 2B2914A023 for ; Wed, 10 Apr 2013 09:06:44 +0200 (CEST) X-RZG-AUTH: :IW0NeWC7b/q2i6W/qstXb1SBUuFnrGohdvpEkce+Ub4+ReKfHD+mCPYMrYBXgQ== X-RZG-CLASS-ID: mo05 Received: from ubuntu-2012.fritz.box (p57B94BB4.dip.t-dialin.net [87.185.75.180]) by smtp.strato.de (joses mo3) (RZmta 31.24 DYNA|AUTH) with ESMTPA id g0799ap3A6F0En ; Wed, 10 Apr 2013 09:06:33 +0200 (CEST) From: Stefan Roese To: u-boot@lists.denx.de Date: Wed, 10 Apr 2013 09:06:09 +0200 Message-Id: <1365577570-12384-4-git-send-email-sr@denx.de> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1365577570-12384-1-git-send-email-sr@denx.de> References: <1365577570-12384-1-git-send-email-sr@denx.de> Cc: Marek Vasut , Fabio Estevam Subject: [U-Boot] [PATCH 3/4] dma: Add i.MX6 support to drivers/dma/apbh_dma.c X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de This will be used by the i.MX6 NAND support. Signed-off-by: Stefan Roese Cc: Stefano Babic Cc: Marek Vasut Cc: Fabio Estevam --- arch/arm/include/asm/arch-mx6/imx-regs.h | 4 ++++ arch/arm/include/asm/imx-common/dma.h | 12 ++++++++++++ arch/arm/include/asm/imx-common/regs-apbh.h | 17 ++++++++++++++++- drivers/dma/apbh_dma.c | 2 +- 4 files changed, 33 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index eaa7439..6837678 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -38,6 +38,10 @@ #define DTCP_ARB_BASE_ADDR 0x00138000 #define DTCP_ARB_END_ADDR 0x0013BFFF +#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR +#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000) +#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) + /* GPV - PL301 configuration ports */ #define GPV2_BASE_ADDR 0x00200000 #define GPV3_BASE_ADDR 0x00300000 diff --git a/arch/arm/include/asm/imx-common/dma.h b/arch/arm/include/asm/imx-common/dma.h index 1ac8696..cb74528 100644 --- a/arch/arm/include/asm/imx-common/dma.h +++ b/arch/arm/include/asm/imx-common/dma.h @@ -72,6 +72,18 @@ enum { MXS_DMA_CHANNEL_AHB_APBH_RESERVED1, MXS_MAX_DMA_CHANNELS, }; +#elif defined(CONFIG_MX6) +enum { + MXS_DMA_CHANNEL_AHB_APBH_GPMI0 = 0, + MXS_DMA_CHANNEL_AHB_APBH_GPMI1, + MXS_DMA_CHANNEL_AHB_APBH_GPMI2, + MXS_DMA_CHANNEL_AHB_APBH_GPMI3, + MXS_DMA_CHANNEL_AHB_APBH_GPMI4, + MXS_DMA_CHANNEL_AHB_APBH_GPMI5, + MXS_DMA_CHANNEL_AHB_APBH_GPMI6, + MXS_DMA_CHANNEL_AHB_APBH_GPMI7, + MXS_MAX_DMA_CHANNELS, +}; #endif /* diff --git a/arch/arm/include/asm/imx-common/regs-apbh.h b/arch/arm/include/asm/imx-common/regs-apbh.h index a5de927..bcec6e0 100644 --- a/arch/arm/include/asm/imx-common/regs-apbh.h +++ b/arch/arm/include/asm/imx-common/regs-apbh.h @@ -109,7 +109,7 @@ struct mxs_apbh_regs { mxs_reg_32(hw_apbh_version) }; -#elif defined(CONFIG_MX28) +#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6)) struct mxs_apbh_regs { mxs_reg_32(hw_apbh_ctrl0) mxs_reg_32(hw_apbh_ctrl1) @@ -288,6 +288,17 @@ struct mxs_apbh_regs { #define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0800 #define APBH_CTRL0_CLKGATE_CHANNEL_HSADC 0x1000 #define APBH_CTRL0_CLKGATE_CHANNEL_LCDIF 0x2000 +#elif defined(CONFIG_MX6) +#define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 0 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x0001 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x0002 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND2 0x0004 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND3 0x0008 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND4 0x0010 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND5 0x0020 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND6 0x0040 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0080 +#define APBH_CTRL0_CLKGATE_CHANNEL_SSP 0x0100 #endif #define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN (1 << 31) @@ -393,6 +404,10 @@ struct mxs_apbh_regs { #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF 0x2000 #endif +#if defined(CONFIG_MX6) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16 +#endif + #if defined(CONFIG_MX23) #define APBH_DEVSEL_CH7_MASK (0xf << 28) #define APBH_DEVSEL_CH7_OFFSET 28 diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c index eb46bcf..510cb28 100644 --- a/drivers/dma/apbh_dma.c +++ b/drivers/dma/apbh_dma.c @@ -227,7 +227,7 @@ static int mxs_dma_reset(int channel) #if defined(CONFIG_MX23) uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_ctrl0_set); uint32_t offset = APBH_CTRL0_RESET_CHANNEL_OFFSET; -#elif defined(CONFIG_MX28) +#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6)) uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_channel_ctrl_set); uint32_t offset = APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET; #endif