Patchwork [net-next,2/2] ixgbe: fix for 82598 Si errata causing buffer overflow

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Submitter Jeff Kirsher
Date Feb. 21, 2009, 10:23 p.m.
Message ID <20090221222339.6451.72721.stgit@lost.foo-projects.org>
Download mbox | patch
Permalink /patch/23521/
State Accepted
Delegated to: David Miller
Headers show

Comments

Jeff Kirsher - Feb. 21, 2009, 10:23 p.m.
From: Don Skidmore <donald.c.skidmore@intel.com>

The failure happens when an interrupt occurs and the driver is reading
EICR.  This read will cause a clear-by-read which leads to two TLP
being inserted in the PCIe retry buffer leading to an overflow of the
buffer and corruption of TLPs.

The solution is different depending where the reading of EICR takes place.

For ixgbe_msix_lsc() since we are in MSIX mode and know OCD is enabled a
clear-by-write is done instead of the normal clear-by-read.

For ixgbe_intr() 0xffffffff is written to EIMC before the read, masking the
interrupts.

Signed-off-by: Don Skidmore <donald.c.skidmore@intel.com>
Acked-by: Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
---

 drivers/net/ixgbe/ixgbe_main.c |   17 ++++++++++++++++-
 1 files changed, 16 insertions(+), 1 deletions(-)


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David Miller - Feb. 21, 2009, 11:43 p.m.
From: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Date: Sat, 21 Feb 2009 14:23:40 -0800

> The failure happens when an interrupt occurs and the driver is reading
> EICR.  This read will cause a clear-by-read which leads to two TLP
> being inserted in the PCIe retry buffer leading to an overflow of the
> buffer and corruption of TLPs.
> 
> The solution is different depending where the reading of EICR takes place.
> 
> For ixgbe_msix_lsc() since we are in MSIX mode and know OCD is enabled a
> clear-by-write is done instead of the normal clear-by-read.
> 
> For ixgbe_intr() 0xffffffff is written to EIMC before the read, masking the
> interrupts.
> 
> Signed-off-by: Don Skidmore <donald.c.skidmore@intel.com>
> Acked-by: Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com>
> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>

Applied, thanks.
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Patch

diff --git a/drivers/net/ixgbe/ixgbe_main.c b/drivers/net/ixgbe/ixgbe_main.c
index a935949..8fbd4c8 100644
--- a/drivers/net/ixgbe/ixgbe_main.c
+++ b/drivers/net/ixgbe/ixgbe_main.c
@@ -937,7 +937,16 @@  static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
 	struct net_device *netdev = data;
 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
 	struct ixgbe_hw *hw = &adapter->hw;
-	u32 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
+	u32 eicr;
+
+	/*
+	 * Workaround for Silicon errata.  Use clear-by-write instead
+	 * of clear-by-read.  Reading with EICS will return the
+	 * interrupt causes without clearing, which later be done
+	 * with the write to EICR.
+	 */
+	eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
+	IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
 
 	if (eicr & IXGBE_EICR_LSC)
 		ixgbe_check_lsc(adapter);
@@ -1356,6 +1365,12 @@  static irqreturn_t ixgbe_intr(int irq, void *data)
 	struct ixgbe_hw *hw = &adapter->hw;
 	u32 eicr;
 
+	/*
+	 * Workaround for silicon errata.  Mask the interrupts
+	 * before the read of EICR.
+	 */
+	IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
+
 	/* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
 	 * therefore no explict interrupt disable is necessary */
 	eicr = IXGBE_READ_REG(hw, IXGBE_EICR);