Patchwork [5/5] drm/i915: PIPE_CONTROL TLB invalidate requires CS stall

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Submitter Luis Henriques
Date April 9, 2013, 4:06 p.m.
Message ID <1365523617-21177-6-git-send-email-luis.henriques@canonical.com>
Download mbox | patch
Permalink /patch/235134/
State New
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Comments

Luis Henriques - April 9, 2013, 4:06 p.m.
From: Jesse Barnes <jbarnes@virtuousgeek.org>

BugLink: http://bugs.launchpad.net/bugs/1140716

"If ENABLED, PIPE_CONTROL command will flush the in flight data  written
out by render engine to Global Observation point on flush done. Also
Requires stall bit ([20] of DW1) set."

So set the stall bit to ensure proper invalidation.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Antti Koskipää <antti.koskipaa@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
(cherry picked from commit 3ac7831314eba873d60b58718123c503f6961337)

Signed-off-by: Luis Henriques <luis.henriques@canonical.com>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Patch

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 32b2458..c3654ff 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -229,7 +229,7 @@  gen6_render_ring_flush(struct intel_ring_buffer *ring,
 		/*
 		 * TLB invalidate requires a post-sync write.
 		 */
-		flags |= PIPE_CONTROL_QW_WRITE;
+		flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 	}
 
 	ret = intel_ring_begin(ring, 4);