Message ID | 1365498400-30558-1-git-send-email-hutao@cn.fujitsu.com |
---|---|
State | New |
Headers | show |
Il 09/04/2013 11:06, Hu Tao ha scritto: > Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> > Signed-off-by: Hu Tao <hutao@cn.fujitsu.com> Thanks, seems like we're good. Please resubmit, the new position for pvpanic.c should be in hw/misc. Paolo > --- > hw/i386/pc_piix.c | 16 ++++++++++++++-- > hw/i386/pc_q35.c | 15 ++++++++++++++- > hw/pc.h | 3 +++ > hw/pvpanic.c | 7 +++++++ > 4 files changed, 38 insertions(+), 3 deletions(-) > > diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c > index 0abc9f1..384c95f 100644 > --- a/hw/i386/pc_piix.c > +++ b/hw/i386/pc_piix.c > @@ -54,6 +54,8 @@ static const int ide_iobase[MAX_IDE_BUS] = { 0x1f0, 0x170 }; > static const int ide_iobase2[MAX_IDE_BUS] = { 0x3f6, 0x376 }; > static const int ide_irq[MAX_IDE_BUS] = { 14, 15 }; > > +static bool has_pvpanic = true; > + > /* PC hardware initialisation */ > static void pc_init1(MemoryRegion *system_memory, > MemoryRegion *system_io, > @@ -217,6 +219,10 @@ static void pc_init1(MemoryRegion *system_memory, > if (pci_enabled) { > pc_pci_device_init(pci_bus); > } > + > + if (has_pvpanic) { > + pvpanic_init(isa_bus); > + } > } > > static void pc_init_pci(QEMUMachineInitArgs *args) > @@ -234,10 +240,16 @@ static void pc_init_pci(QEMUMachineInitArgs *args) > initrd_filename, cpu_model, 1, 1); > } > > +static void pc_init_pci_1_4(QEMUMachineInitArgs *args) > +{ > + has_pvpanic = false; > + pc_init_pci(args); > +} > + > static void pc_init_pci_1_3(QEMUMachineInitArgs *args) > { > enable_compat_apic_id_mode(); > - pc_init_pci(args); > + pc_init_pci_1_4(args); > } > > /* PC machine init function for pc-0.14 to pc-1.2 */ > @@ -308,7 +320,7 @@ static QEMUMachine pc_i440fx_machine_v1_5 = { > static QEMUMachine pc_i440fx_machine_v1_4 = { > .name = "pc-i440fx-1.4", > .desc = "Standard PC (i440FX + PIIX, 1996)", > - .init = pc_init_pci, > + .init = pc_init_pci_1_4, > .max_cpus = 255, > .compat_props = (GlobalProperty[]) { > PC_COMPAT_1_4, > diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c > index 4f5f347..7f9b65f 100644 > --- a/hw/i386/pc_q35.c > +++ b/hw/i386/pc_q35.c > @@ -45,6 +45,8 @@ > /* ICH9 AHCI has 6 ports */ > #define MAX_SATA_PORTS 6 > > +static bool has_pvpanic = true; > + > /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE) > * BIOS will read it and start S3 resume at POST Entry */ > static void pc_cmos_set_s3_resume(void *opaque, int irq, int level) > @@ -207,8 +209,19 @@ static void pc_q35_init(QEMUMachineInitArgs *args) > if (pci_enabled) { > pc_pci_device_init(host_bus); > } > + > + if (has_pvpanic) { > + pvpanic_init(isa_bus); > + } > +} > + > +static void pc_q35_init_1_4(QEMUMachineInitArgs *args) > +{ > + has_pvpanic = false; > + pc_q35_init(args); > } > > + > static QEMUMachine pc_q35_machine_v1_5 = { > .name = "pc-q35-1.5", > .alias = "q35", > @@ -221,7 +234,7 @@ static QEMUMachine pc_q35_machine_v1_5 = { > static QEMUMachine pc_q35_machine_v1_4 = { > .name = "pc-q35-1.4", > .desc = "Standard PC (Q35 + ICH9, 2009)", > - .init = pc_q35_init, > + .init = pc_q35_init_1_4, > .max_cpus = 255, > .compat_props = (GlobalProperty[]) { > PC_COMPAT_1_4, > diff --git a/hw/pc.h b/hw/pc.h > index 8e1dd4c..912baf5 100644 > --- a/hw/pc.h > +++ b/hw/pc.h > @@ -178,6 +178,9 @@ static inline bool isa_ne2000_init(ISABus *bus, int base, int irq, NICInfo *nd) > /* pc_sysfw.c */ > void pc_system_firmware_init(MemoryRegion *rom_memory); > > +/* pvpanic.c */ > +int pvpanic_init(ISABus *bus); > + > /* e820 types */ > #define E820_RAM 1 > #define E820_RESERVED 2 > diff --git a/hw/pvpanic.c b/hw/pvpanic.c > index b3d10e2..bb30207 100644 > --- a/hw/pvpanic.c > +++ b/hw/pvpanic.c > @@ -19,6 +19,7 @@ > #include <sysemu/kvm.h> > > #include "hw/fw_cfg.h" > +#include "hw/pc.h" > > /* The bit of supported pv event */ > #define PVPANIC_F_PANICKED 0 > @@ -100,6 +101,12 @@ static int pvpanic_isa_initfn(ISADevice *dev) > return 0; > } > > +int pvpanic_init(ISABus *bus) > +{ > + isa_create_simple(bus, TYPE_ISA_PVPANIC_DEVICE); > + return 0; > +} > + > static Property pvpanic_isa_properties[] = { > DEFINE_PROP_UINT16("ioport", PVPanicState, ioport, 0x505), > DEFINE_PROP_END_OF_LIST(), >
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 0abc9f1..384c95f 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -54,6 +54,8 @@ static const int ide_iobase[MAX_IDE_BUS] = { 0x1f0, 0x170 }; static const int ide_iobase2[MAX_IDE_BUS] = { 0x3f6, 0x376 }; static const int ide_irq[MAX_IDE_BUS] = { 14, 15 }; +static bool has_pvpanic = true; + /* PC hardware initialisation */ static void pc_init1(MemoryRegion *system_memory, MemoryRegion *system_io, @@ -217,6 +219,10 @@ static void pc_init1(MemoryRegion *system_memory, if (pci_enabled) { pc_pci_device_init(pci_bus); } + + if (has_pvpanic) { + pvpanic_init(isa_bus); + } } static void pc_init_pci(QEMUMachineInitArgs *args) @@ -234,10 +240,16 @@ static void pc_init_pci(QEMUMachineInitArgs *args) initrd_filename, cpu_model, 1, 1); } +static void pc_init_pci_1_4(QEMUMachineInitArgs *args) +{ + has_pvpanic = false; + pc_init_pci(args); +} + static void pc_init_pci_1_3(QEMUMachineInitArgs *args) { enable_compat_apic_id_mode(); - pc_init_pci(args); + pc_init_pci_1_4(args); } /* PC machine init function for pc-0.14 to pc-1.2 */ @@ -308,7 +320,7 @@ static QEMUMachine pc_i440fx_machine_v1_5 = { static QEMUMachine pc_i440fx_machine_v1_4 = { .name = "pc-i440fx-1.4", .desc = "Standard PC (i440FX + PIIX, 1996)", - .init = pc_init_pci, + .init = pc_init_pci_1_4, .max_cpus = 255, .compat_props = (GlobalProperty[]) { PC_COMPAT_1_4, diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 4f5f347..7f9b65f 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -45,6 +45,8 @@ /* ICH9 AHCI has 6 ports */ #define MAX_SATA_PORTS 6 +static bool has_pvpanic = true; + /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE) * BIOS will read it and start S3 resume at POST Entry */ static void pc_cmos_set_s3_resume(void *opaque, int irq, int level) @@ -207,8 +209,19 @@ static void pc_q35_init(QEMUMachineInitArgs *args) if (pci_enabled) { pc_pci_device_init(host_bus); } + + if (has_pvpanic) { + pvpanic_init(isa_bus); + } +} + +static void pc_q35_init_1_4(QEMUMachineInitArgs *args) +{ + has_pvpanic = false; + pc_q35_init(args); } + static QEMUMachine pc_q35_machine_v1_5 = { .name = "pc-q35-1.5", .alias = "q35", @@ -221,7 +234,7 @@ static QEMUMachine pc_q35_machine_v1_5 = { static QEMUMachine pc_q35_machine_v1_4 = { .name = "pc-q35-1.4", .desc = "Standard PC (Q35 + ICH9, 2009)", - .init = pc_q35_init, + .init = pc_q35_init_1_4, .max_cpus = 255, .compat_props = (GlobalProperty[]) { PC_COMPAT_1_4, diff --git a/hw/pc.h b/hw/pc.h index 8e1dd4c..912baf5 100644 --- a/hw/pc.h +++ b/hw/pc.h @@ -178,6 +178,9 @@ static inline bool isa_ne2000_init(ISABus *bus, int base, int irq, NICInfo *nd) /* pc_sysfw.c */ void pc_system_firmware_init(MemoryRegion *rom_memory); +/* pvpanic.c */ +int pvpanic_init(ISABus *bus); + /* e820 types */ #define E820_RAM 1 #define E820_RESERVED 2 diff --git a/hw/pvpanic.c b/hw/pvpanic.c index b3d10e2..bb30207 100644 --- a/hw/pvpanic.c +++ b/hw/pvpanic.c @@ -19,6 +19,7 @@ #include <sysemu/kvm.h> #include "hw/fw_cfg.h" +#include "hw/pc.h" /* The bit of supported pv event */ #define PVPANIC_F_PANICKED 0 @@ -100,6 +101,12 @@ static int pvpanic_isa_initfn(ISADevice *dev) return 0; } +int pvpanic_init(ISABus *bus) +{ + isa_create_simple(bus, TYPE_ISA_PVPANIC_DEVICE); + return 0; +} + static Property pvpanic_isa_properties[] = { DEFINE_PROP_UINT16("ioport", PVPanicState, ioport, 0x505), DEFINE_PROP_END_OF_LIST(),