From patchwork Mon Apr 8 05:08:20 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 234573 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id B36FD2C00BF for ; Mon, 8 Apr 2013 15:15:10 +1000 (EST) Received: from localhost ([::1]:58974 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UP4Q8-00033W-On for incoming@patchwork.ozlabs.org; Mon, 08 Apr 2013 01:15:08 -0400 Received: from eggs.gnu.org ([208.118.235.92]:40641) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UP4PO-0002j5-8U for qemu-devel@nongnu.org; Mon, 08 Apr 2013 01:14:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UP4P6-0003bJ-Na for qemu-devel@nongnu.org; Mon, 08 Apr 2013 01:14:22 -0400 Received: from ozlabs.org ([2402:b800:7003:1:1::1]:40125) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UP4P6-0003b4-CG; Mon, 08 Apr 2013 01:14:04 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id A570E2C00CB; Mon, 8 Apr 2013 15:14:00 +1000 (EST) From: David Gibson To: agraf@suse.de Date: Mon, 8 Apr 2013 15:08:20 +1000 Message-Id: <1365397702-1515-6-git-send-email-david@gibson.dropbear.id.au> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1365397702-1515-1-git-send-email-david@gibson.dropbear.id.au> References: <1365397702-1515-1-git-send-email-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2402:b800:7003:1:1::1 Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, David Gibson Subject: [Qemu-devel] [PATCH 5/7] target-ppc: Add more stubs for POWER7 PMU registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org In addition to the performance monitor registers found on nearly all 6xx chips, the POWER7 has two additional counters (PMC5 & PMC6) and an extra control register (MMCRA). This patch adds stub support for them to qemu - the registers won't do anything, but with this change won't cause illegal instruction traps accessing them. They're also registered with their ONE_REG ids, so their value will be kept in sync with KVM where appropriate. Signed-off-by: David Gibson --- target-ppc/cpu.h | 1 + target-ppc/translate_init.c | 12 ++++++++++++ 2 files changed, 13 insertions(+) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 42c36e2..94bd36b 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1446,6 +1446,7 @@ static inline void cpu_clone_regs(CPUPPCState *env, target_ulong newsp) #define SPR_PERF2 (0x302) #define SPR_RCPU_MI_RBA2 (0x302) #define SPR_MPC_MI_AP (0x302) +#define SPR_MMCRA (0x302) #define SPR_PERF3 (0x303) #define SPR_RCPU_MI_RBA3 (0x303) #define SPR_MPC_MI_EPN (0x303) diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 6e20b55..71e434a 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -6962,6 +6962,18 @@ static void init_proc_POWER7 (CPUPPCState *env) SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, KVM_REG_PPC_DSCR, 0x00000000); + spr_register_kvm(env, SPR_MMCRA, "SPR_MMCRA", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_MMCRA, 0x00000000); + spr_register_kvm(env, SPR_PMC5, "SPR_PMC5", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_PMC5, 0x00000000); + spr_register_kvm(env, SPR_PMC6, "SPR_PMC6", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_PMC6, 0x00000000); #endif /* !CONFIG_USER_ONLY */ /* Memory management */ /* XXX : not implemented */