@@ -101,6 +101,7 @@ static void icp_set_cppr(struct icp_state *icp, int server, uint8_t cppr)
if (XISR(ss) && (cppr <= ss->pending_priority)) {
old_xisr = XISR(ss);
ss->xirr &= ~XISR_MASK; /* Clear XISR */
+ ss->pending_priority = 0xff;
qemu_irq_lower(ss->output);
ics_reject(icp->ics, old_xisr);
}
@@ -127,6 +128,7 @@ static uint32_t icp_accept(struct icp_server_state *ss)
qemu_irq_lower(ss->output);
ss->xirr = ss->pending_priority << 24;
+ ss->pending_priority = 0xff;
trace_xics_icp_accept(xirr, ss->xirr);
Under certain circumstances the emulation for the pseries "XICS" interrupt controller was clearing a pending interrupt from the XISR register, without also clearing the corresponding priority variable. This will cause problems later when can trigger sanity checks in the under-development in-kernel XICS implementation. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> --- hw/ppc/xics.c | 2 ++ 1 file changed, 2 insertions(+)