Index: config.gcc
===================================================================
--- config.gcc	(revision 197536)
+++ config.gcc	(working copy)
@@ -3694,7 +3694,6 @@ case ${target} in
 		;;
 
 	hppa*-*-*)
-		target_cpu_default2="MASK_BIG_SWITCH"
 		if test x$gas = xyes
 		then
 			target_cpu_default2="${target_cpu_default2}|MASK_GAS|MASK_JUMP_IN_DELAY"
Index: config/pa/pa.opt
===================================================================
--- config/pa/pa.opt	(revision 197536)
+++ config/pa/pa.opt	(working copy)
@@ -38,8 +38,8 @@ Target RejectNegative
 Generate PA2.0 code (requires binutils 2.10 or later)
 
 mbig-switch
-Target Report Mask(BIG_SWITCH)
-Generate code for huge switch statements
+Target Ignore
+Does nothing.  Preserved for backward compatibility.
 
 mdisable-fpregs
 Target Report Mask(DISABLE_FPREGS)
Index: config/pa/pa.h
===================================================================
--- config/pa/pa.h	(revision 197536)
+++ config/pa/pa.h	(working copy)
@@ -114,7 +114,7 @@ extern unsigned long total_code_bytes;
 #define TARGET_HPUX_UNWIND_LIBRARY 0
 
 #ifndef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_GAS | MASK_JUMP_IN_DELAY | MASK_BIG_SWITCH)
+#define TARGET_DEFAULT (MASK_GAS | MASK_JUMP_IN_DELAY)
 #endif
 
 #ifndef TARGET_CPU_DEFAULT
@@ -984,11 +984,10 @@ do {									     \
 #define FUNCTION_NAME_P(NAME)  (*(NAME) == '@')
 
-/* Specify the machine mode that this machine uses for the index in the
-   tablejump instruction.  For small tables, an element consists of a
-   ia-relative branch and its delay slot.  When -mbig-switch is specified,
-   we use a 32-bit absolute address for non-pic code, and a 32-bit offset
-   for both 32 and 64-bit pic code.  */
-#define CASE_VECTOR_MODE (TARGET_BIG_SWITCH ? SImode : DImode)
+/* Specify the machine mode that this machine uses for the index in the
+   tablejump instruction.  
+   We use a 32-bit absolute address for non-pic code, and a 32-bit offset
+   for both 32 and 64-bit pic code.  */
+#define CASE_VECTOR_MODE SImode
 
 /* Jump tables must be 32-bit aligned, no matter the size of the element.  */
 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
@@ -1165,8 +1164,8 @@ do {									     \
   pa_output_ascii ((FILE), (P), (SIZE))
 
 /* Jump tables are always placed in the text section.  Technically, it
-   is possible to put them in the readonly data section when -mbig-switch
-   is specified.  This has the benefit of getting the table out of .text
+   is possible to put them in the readonly data section.
+   This has the benefit of getting the table out of .text
    and reducing branch lengths as a result.  The downside is that an
    additional insn (addil) is needed to access the table when generating
    PIC code.  The address difference table also has to use 32-bit
@@ -1182,20 +1181,14 @@ do {									     \
 /* This is how to output an element of a case-vector that is absolute.  */
 
 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)  \
-  if (TARGET_BIG_SWITCH)						\
     fprintf (FILE, "\t.word L$%04d\n", VALUE);				\
-  else									\
-    fprintf (FILE, "\tb L$%04d\n\tnop\n", VALUE)
 
 /* This is how to output an element of a case-vector that is relative. 
    Since we always place jump tables in the text section, the difference
    is absolute and requires no relocation.  */
 
 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)  \
-  if (TARGET_BIG_SWITCH)						\
     fprintf (FILE, "\t.word L$%04d-L$%04d\n", VALUE, REL);		\
-  else									\
-    fprintf (FILE, "\tb L$%04d\n\tnop\n", VALUE)
 
 /* This is how to output an assembler line that says to advance the
    location counter to a multiple of 2**LOG bytes.  */
Index: config/pa/pa-linux.h
===================================================================
--- config/pa/pa-linux.h	(revision 197536)
+++ config/pa/pa-linux.h	(working copy)
@@ -78,17 +78,11 @@ along with GCC; see the file COPYING3.
 
 #undef ASM_OUTPUT_ADDR_VEC_ELT
 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
-  if (TARGET_BIG_SWITCH)					\
     fprintf (FILE, "\t.word .L%d\n", VALUE);			\
-  else								\
-    fprintf (FILE, "\tb .L%d\n\tnop\n", VALUE)
 
 #undef ASM_OUTPUT_ADDR_DIFF_ELT
 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
-  if (TARGET_BIG_SWITCH)					\
     fprintf (FILE, "\t.word .L%d-.L%d\n", VALUE, REL);		\
-  else								\
-    fprintf (FILE, "\tb .L%d\n\tnop\n", VALUE)
 
 /* Use the default.  */
 #undef ASM_OUTPUT_LABEL
Index: config/pa/pa-openbsd.h
===================================================================
--- config/pa/pa-openbsd.h	(revision 197536)
+++ config/pa/pa-openbsd.h	(working copy)
@@ -49,17 +49,11 @@ along with GCC; see the file COPYING3.
 
 #undef ASM_OUTPUT_ADDR_VEC_ELT
 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
-  if (TARGET_BIG_SWITCH)					\
     fprintf (FILE, "\t.word .L%d\n", VALUE);			\
-  else								\
-    fprintf (FILE, "\tb .L%d\n\tnop\n", VALUE)
 
 #undef ASM_OUTPUT_ADDR_DIFF_ELT
 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
-  if (TARGET_BIG_SWITCH)					\
     fprintf (FILE, "\t.word .L%d-.L%d\n", VALUE, REL);		\
-  else								\
-    fprintf (FILE, "\tb .L%d\n\tnop\n", VALUE)
 
 /* Use the default.  */
 #undef ASM_OUTPUT_LABEL
Index: config/pa/pa-hpux.h
===================================================================
--- config/pa/pa-hpux.h	(revision 197536)
+++ config/pa/pa-hpux.h	(working copy)
@@ -25,7 +25,7 @@ along with GCC; see the file COPYING3.
 #define HPUX_LONG_DOUBLE_LIBRARY 1
 
 #undef TARGET_DEFAULT
-#define TARGET_DEFAULT MASK_BIG_SWITCH
+#define TARGET_DEFAULT 0
 
 /* Make GCC agree with types.h.  */
 #undef SIZE_TYPE
Index: config/pa/pa.md
===================================================================
--- config/pa/pa.md	(revision 197536)
+++ config/pa/pa.md	(working copy)
@@ -6959,16 +6959,6 @@
   [(set_attr "type" "branch")
    (set_attr "length" "4")])
 
-;;; This jump is used in branch tables where the insn length is fixed.
-;;; The length of this insn is adjusted if the delay slot is not filled.
-(define_insn "short_jump"
-  [(set (pc) (label_ref (match_operand 0 "" "")))
-   (const_int 0)]
-  ""
-  "b%* %l0%#"
-  [(set_attr "type" "btable_branch")
-   (set_attr "length" "4")])
-
 ;; Subroutines of "casesi".
 ;; operand 0 is index
 ;; operand 1 is the minimum bound
@@ -7028,34 +7018,16 @@
       operands[0] = index;
     }
 
-  if (TARGET_BIG_SWITCH)
-    {
-      if (TARGET_64BIT)
-	emit_jump_insn (gen_casesi64p (operands[0], operands[3]));
-      else if (flag_pic)
-	emit_jump_insn (gen_casesi32p (operands[0], operands[3]));
-      else
-	emit_jump_insn (gen_casesi32 (operands[0], operands[3]));
-    }
-  else
-    emit_jump_insn (gen_casesi0 (operands[0], operands[3]));
+  if (TARGET_64BIT)
+    emit_jump_insn (gen_casesi64p (operands[0], operands[3]));
+  else if (flag_pic)
+    emit_jump_insn (gen_casesi32p (operands[0], operands[3]));
+  else
+    emit_jump_insn (gen_casesi32 (operands[0], operands[3]));
+
   DONE;
 }")
 
-;;; The rtl for this pattern doesn't accurately describe what the insn
-;;; actually does, particularly when case-vector elements are exploded
-;;; in pa_reorg.  However, the initial SET in these patterns must show
-;;; the connection of the insn to the following jump table.
-(define_insn "casesi0"
-  [(set (pc) (mem:SI (plus:SI
-		       (mult:SI (match_operand:SI 0 "register_operand" "r")
-				(const_int 4))
-		       (label_ref (match_operand 1 "" "")))))]
-  ""
-  "blr,n %0,%%r0\;nop"
-  [(set_attr "type" "multi")
-   (set_attr "length" "8")])
-
 ;;; 32-bit code, absolute branch table.
 (define_insn "casesi32"
   [(set (pc) (mem:SI (plus:SI
Index: config/pa/pa.c
===================================================================
--- config/pa/pa.c	(revision 197536)
+++ config/pa/pa.c	(working copy)
@@ -101,7 +101,7 @@ static void compute_zdepdi_operands (uns
 static int compute_movmem_length (rtx);
 static int compute_clrmem_length (rtx);
 static bool pa_assemble_integer (rtx, unsigned int, int);
-static void remove_useless_addtr_insns (int);
+static void remove_useless_addtr_insns (bool);
 static void store_reg (int, HOST_WIDE_INT, int);
 static void store_reg_modify (int, int, HOST_WIDE_INT);
 static void load_reg (int, HOST_WIDE_INT, int);
@@ -3292,20 +3292,16 @@ pa_output_ascii (FILE *file, const char
 /* Try to rewrite floating point comparisons & branches to avoid
    useless add,tr insns.
 
-   CHECK_NOTES is nonzero if we should examine REG_DEAD notes
-   to see if FPCC is dead.  CHECK_NOTES is nonzero for the
-   first attempt to remove useless add,tr insns.  It is zero
-   for the second pass as reorg sometimes leaves bogus REG_DEAD
-   notes lying around.
-
-   When CHECK_NOTES is zero we can only eliminate add,tr insns
-   when there's a 1:1 correspondence between fcmp and ftest/fbranch
-   instructions.  */
-static void
-remove_useless_addtr_insns (int check_notes)
+   CHECK_NOTES is true if we should examine REG_DEAD notes
+   to see if FPCC is dead.  CHECK_NOTES is true for the
+   first attempt to remove useless add,tr insns.  It is false
+   for the second pass as reorg sometimes leaves bogus REG_DEAD
+   notes lying around.  */
+
+static void
+remove_useless_addtr_insns (bool check_notes)
 {
   rtx insn;
-  static int pass = 0;
 
   /* This is fairly cheap, so always run it when optimizing.  */
   if (optimize > 0)
@@ -3352,6 +3348,12 @@ remove_useless_addtr_insns (int check_no
 	}
 
 
+      /* When CHECK_NOTES is false we can only eliminate add,tr insns
+	 when there's a 1:1 correspondence between fcmp and ftest/fbranch
+	 instructions.  */
+      if (! check_notes && fcmp_count != fbranch_count)
+	return;
+
       /* Find all floating point compare + branch insns.  If possible,
 	 reverse the comparison & the branch to avoid add,tr insns.  */
       for (insn = get_insns (); insn; insn = next_insn (insn))
@@ -3410,8 +3412,8 @@ remove_useless_addtr_insns (int check_no
 		  && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
 		  && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
 		  && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
-		  && (fcmp_count == fbranch_count
-		      || (check_notes
+		  && (! check_notes
+		      || (check_notes 
 			  && find_regno_note (next, REG_DEAD, 0))))
 		{
 		  /* Reverse the branch.  */
@@ -3429,9 +3431,6 @@ remove_useless_addtr_insns (int check_no
 	    }
 	}
     }
-
-  pass = !pass;
-
 }
 
 /* You may have trouble believing this, but this is the 32 bit HP-PA
@@ -3777,7 +3776,7 @@ pa_output_function_prologue (FILE *file,
 
   fputs ("\n\t.ENTRY\n", file);
 
-  remove_useless_addtr_insns (0);
+  remove_useless_addtr_insns (/*check_notes=*/false);
 }
 
 void
@@ -8945,35 +8944,8 @@ pa_following_call (rtx insn)
 /* We use this hook to perform a PA specific optimization which is difficult
    to do in earlier passes.
 
-   We want the delay slots of branches within jump tables to be filled.
-   None of the compiler passes at the moment even has the notion that a
-   PA jump table doesn't contain addresses, but instead contains actual
-   instructions!
-
-   Because we actually jump into the table, the addresses of each entry
-   must stay constant in relation to the beginning of the table (which
-   itself must stay constant relative to the instruction to jump into
-   it).  I don't believe we can guarantee earlier passes of the compiler
-   will adhere to those rules.
-
-   So, late in the compilation process we find all the jump tables, and
-   expand them into real code -- e.g. each entry in the jump table vector
-   will get an appropriate label followed by a jump to the final target.
-
-   Reorg and the final jump pass can then optimize these branches and
-   fill their delay slots.  We end up with smaller, more efficient code.
-
-   The jump instructions within the table are special; we must be able
-   to identify them during assembly output (if the jumps don't get filled
-   we need to emit a nop rather than nullifying the delay slot)).  We
-   identify jumps in switch tables by using insns with the attribute
-   type TYPE_BTABLE_BRANCH.
-
-   We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
-   insns.  This serves two purposes, first it prevents jump.c from
-   noticing that the last N entries in the table jump to the instruction
-   immediately after the table and deleting the jumps.  Second, those
-   insns mark where we should emit .begin_brtab and .end_brtab directives
+   We surround jump table data with BEGIN_BRTAB and END_BRTAB pseudo-insns,
+   which mark where we should emit .begin_brtab and .end_brtab directives
    when using GAS (allows for better link time optimizations).  */
 
 static void
@@ -8981,87 +8953,27 @@ pa_reorg (void)
 {
   rtx insn;
 
-  remove_useless_addtr_insns (1);
+  remove_useless_addtr_insns (/*check_notes=*/true);
 
   if (pa_cpu < PROCESSOR_8000)
     pa_combine_instructions ();
 
-
-  /* This is fairly cheap, so always run it if optimizing.  */
-  if (optimize > 0 && !TARGET_BIG_SWITCH)
-    {
-      /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns.  */
-      for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
-	{
-	  rtx pattern, tmp, location, label;
-	  unsigned int length, i;
-
-	  /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode.  */
-	  if (! JUMP_TABLE_DATA_P (insn))
-	    continue;
-
-	  /* Emit marker for the beginning of the branch table.  */
-	  emit_insn_before (gen_begin_brtab (), insn);
-
-	  pattern = PATTERN (insn);
-	  location = PREV_INSN (insn);
-          length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC);
-
-	  for (i = 0; i < length; i++)
-	    {
-	      /* Emit a label before each jump to keep jump.c from
-		 removing this code.  */
-	      tmp = gen_label_rtx ();
-	      LABEL_NUSES (tmp) = 1;
-	      emit_label_after (tmp, location);
-	      location = NEXT_INSN (location);
-
-	      if (GET_CODE (pattern) == ADDR_VEC)
-		label = XEXP (XVECEXP (pattern, 0, i), 0);
-	      else
-		label = XEXP (XVECEXP (pattern, 1, i), 0);
-
-	      tmp = gen_short_jump (label);
-
-	      /* Emit the jump itself.  */
-	      tmp = emit_jump_insn_after (tmp, location);
-	      JUMP_LABEL (tmp) = label;
-	      LABEL_NUSES (label)++;
-	      location = NEXT_INSN (location);
-
-	      /* Emit a BARRIER after the jump.  */
-	      emit_barrier_after (location);
-	      location = NEXT_INSN (location);
-	    }
-
-	  /* Emit marker for the end of the branch table.  */
-	  emit_insn_before (gen_end_brtab (), location);
-	  location = NEXT_INSN (location);
-	  emit_barrier_after (location);
-
-	  /* Delete the ADDR_VEC or ADDR_DIFF_VEC.  */
-	  delete_insn (insn);
-	}
-    }
-  else
-    {
-      /* Still need brtab marker insns.  FIXME: the presence of these
-	 markers disables output of the branch table to readonly memory,
-	 and any alignment directives that might be needed.  Possibly,
-	 the begin_brtab insn should be output before the label for the
-	 table.  This doesn't matter at the moment since the tables are
-	 always output in the text section.  */
-      for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
-	{
-	  /* Find an ADDR_VEC insn.  */
-	  if (! JUMP_TABLE_DATA_P (insn))
-	    continue;
-
-	  /* Now generate markers for the beginning and end of the
-	     branch table.  */
-	  emit_insn_before (gen_begin_brtab (), insn);
-	  emit_insn_after (gen_end_brtab (), insn);
-	}
+  /* Emit brtab marker insns.  FIXME: the presence of these
+     markers disables output of the branch table to readonly memory,
+     and any alignment directives that might be needed.  Possibly,
+     the begin_brtab insn should be output before the label for the
+     table.  This doesn't matter at the moment since the tables are
+     always output in the text section.  */
+  for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
+    {
+      /* Find an ADDR_VEC insn.  */
+      if (! JUMP_TABLE_DATA_P (insn))
+	continue;
+
+      /* Now generate markers for the beginning and end of the
+	 branch table.  */
+      emit_insn_before (gen_begin_brtab (), insn);
+      emit_insn_after (gen_end_brtab (), insn);
     }
 }
 
Index: doc/invoke.texi
===================================================================
--- doc/invoke.texi	(revision 197536)
+++ doc/invoke.texi	(working copy)
@@ -617,11 +617,11 @@ Objective-C and Objective-C++ Dialects}.
 
 @emph{HPPA Options}
 @gccoptlist{-march=@var{architecture-type} @gol
--mbig-switch  -mdisable-fpregs  -mdisable-indexing @gol
+-mdisable-fpregs  -mdisable-indexing @gol
 -mfast-indirect-calls  -mgas  -mgnu-ld   -mhp-ld @gol
 -mfixed-range=@var{register-range} @gol
 -mjump-in-delay -mlinker-opt -mlong-calls @gol
--mlong-load-store  -mno-big-switch  -mno-disable-fpregs @gol
+-mlong-load-store  -mno-disable-fpregs @gol
 -mno-disable-indexing  -mno-fast-indirect-calls  -mno-gas @gol
 -mno-jump-in-delay  -mno-long-load-store @gol
 -mno-portable-runtime  -mno-soft-float @gol
@@ -13433,12 +13433,6 @@ other way around.
 @opindex mpa-risc-2-0
 Synonyms for @option{-march=1.0}, @option{-march=1.1}, and @option{-march=2.0} respectively.
 
-@item -mbig-switch
-@opindex mbig-switch
-Generate code suitable for big switch tables.  Use this option only if
-the assembler/linker complain about out-of-range branches within a switch
-table.
-
 @item -mjump-in-delay
 @opindex mjump-in-delay
 Fill delay slots of function calls with unconditional jump instructions
