From patchwork Fri Apr 5 18:47:35 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 234254 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 31F782C00C3 for ; Sat, 6 Apr 2013 05:53:00 +1100 (EST) Received: from localhost ([::1]:35676 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UOBkw-0004xR-Cj for incoming@patchwork.ozlabs.org; Fri, 05 Apr 2013 14:52:58 -0400 Received: from eggs.gnu.org ([208.118.235.92]:51457) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UOBgb-0005CE-48 for qemu-devel@nongnu.org; Fri, 05 Apr 2013 14:48:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UOBgW-0003qj-Me for qemu-devel@nongnu.org; Fri, 05 Apr 2013 14:48:29 -0400 Received: from mail-qc0-x229.google.com ([2607:f8b0:400d:c01::229]:46274) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UOBgW-0003qd-Iv for qemu-devel@nongnu.org; Fri, 05 Apr 2013 14:48:24 -0400 Received: by mail-qc0-f169.google.com with SMTP id t2so213879qcq.28 for ; Fri, 05 Apr 2013 11:48:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=4TInB70AX28NWmpanUXQ9ADnfq4RTY0B1kSB4XDVnY4=; b=cjSPXQCt6Z9iH0XyT8Qh7y9/nJ7ZEYuV/UqPl3uYo6gsV2x7B4Gq2pD1BcYKGB+Lu+ s1tpZhDNlCwZ2TgEwL9CT1c4Kv7N2eMCBQGKCFoUNj7OACPtS+lMhZy+ceMutVT4ICcI pJDQ0XCnANF2yGxk/KifHfa2ZanoxfkkimZRQOy85OR+mGm56nr/RIjmdM0xMVZbxTaH 1ouMKJ9ibA6uYHnOHNWoc2Fo/gXyBsh8l1rLKMZFpb0IA9HdOUyvWw9tOqjpzkp0i7EZ bLCPu7owW5aES6woiCZDjAV/bP3jxp0Ew8r+/w9HyZawcCQzmpyzCG5bewX16iJhF/Xv sE1Q== X-Received: by 10.229.134.82 with SMTP id i18mr2712221qct.92.1365187704121; Fri, 05 Apr 2013 11:48:24 -0700 (PDT) Received: from pebble.com (107-1-53-7-ip-static.hfc.comcastbusiness.net. [107.1.53.7]) by mx.google.com with ESMTPS id k8sm14592771qej.2.2013.04.05.11.48.22 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Fri, 05 Apr 2013 11:48:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 5 Apr 2013 13:47:35 -0500 Message-Id: <1365187661-17023-8-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1365187661-17023-1-git-send-email-rth@twiddle.net> References: <1365187661-17023-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400d:c01::229 Cc: aliguori@us.ibm.com, aurelien@aurel32.net Subject: [Qemu-devel] [PULL v2 07/13] tcg-s390: Implement deposit opcodes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.c | 24 ++++++++++++++++++++++++ tcg/s390/tcg-target.h | 8 ++++++-- 2 files changed, 30 insertions(+), 2 deletions(-) diff --git a/tcg/s390/tcg-target.c b/tcg/s390/tcg-target.c index dbe2fa6..673a568 100644 --- a/tcg/s390/tcg-target.c +++ b/tcg/s390/tcg-target.c @@ -125,6 +125,7 @@ typedef enum S390Opcode { RIE_CLGIJ = 0xec7d, RIE_CLRJ = 0xec77, RIE_CRJ = 0xec76, + RIE_RISBG = 0xec55, RRE_AGR = 0xb908, RRE_ALGR = 0xb90a, @@ -1206,6 +1207,23 @@ static void tgen_movcond(TCGContext *s, TCGType type, TCGCond c, TCGReg dest, } } +bool tcg_target_deposit_valid(int ofs, int len) +{ + return (facilities & FACILITY_GEN_INST_EXT) != 0; +} + +static void tgen_deposit(TCGContext *s, TCGReg dest, TCGReg src, + int ofs, int len) +{ + int lsb = (63 - ofs); + int msb = lsb - (len - 1); + + /* Format RIE-f */ + tcg_out16(s, (RIE_RISBG & 0xff00) | (dest << 4) | src); + tcg_out16(s, (msb << 8) | lsb); + tcg_out16(s, (ofs << 8) | (RIE_RISBG & 0xff)); +} + static void tgen_gotoi(TCGContext *s, int cc, tcg_target_long dest) { tcg_target_long off = (dest - (tcg_target_long)s->code_ptr) >> 1; @@ -2103,6 +2121,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_qemu_ld(s, args, LD_INT32); break; + OP_32_64(deposit): + tgen_deposit(s, args[0], args[2], args[3], args[4]); + break; + default: fprintf(stderr,"unimplemented opc 0x%x\n",opc); tcg_abort(); @@ -2161,6 +2183,7 @@ static const TCGTargetOpDef s390_op_defs[] = { { INDEX_op_brcond_i32, { "r", "rWC" } }, { INDEX_op_setcond_i32, { "r", "r", "rWC" } }, { INDEX_op_movcond_i32, { "r", "r", "rWC", "r", "0" } }, + { INDEX_op_deposit_i32, { "r", "0", "r" } }, { INDEX_op_qemu_ld8u, { "r", "L" } }, { INDEX_op_qemu_ld8s, { "r", "L" } }, @@ -2228,6 +2251,7 @@ static const TCGTargetOpDef s390_op_defs[] = { { INDEX_op_brcond_i64, { "r", "rC" } }, { INDEX_op_setcond_i64, { "r", "r", "rC" } }, { INDEX_op_movcond_i64, { "r", "r", "rC", "r", "0" } }, + { INDEX_op_deposit_i64, { "r", "0", "r" } }, { INDEX_op_qemu_ld32u, { "r", "L" } }, { INDEX_op_qemu_ld32s, { "r", "L" } }, diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 5e1ac8b..42ca36c 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -63,7 +63,7 @@ typedef enum TCGReg { #define TCG_TARGET_HAS_eqv_i32 0 #define TCG_TARGET_HAS_nand_i32 0 #define TCG_TARGET_HAS_nor_i32 0 -#define TCG_TARGET_HAS_deposit_i32 0 +#define TCG_TARGET_HAS_deposit_i32 1 #define TCG_TARGET_HAS_movcond_i32 1 #define TCG_TARGET_HAS_add2_i32 1 #define TCG_TARGET_HAS_sub2_i32 1 @@ -88,13 +88,17 @@ typedef enum TCGReg { #define TCG_TARGET_HAS_eqv_i64 0 #define TCG_TARGET_HAS_nand_i64 0 #define TCG_TARGET_HAS_nor_i64 0 -#define TCG_TARGET_HAS_deposit_i64 0 +#define TCG_TARGET_HAS_deposit_i64 1 #define TCG_TARGET_HAS_movcond_i64 1 #define TCG_TARGET_HAS_add2_i64 1 #define TCG_TARGET_HAS_sub2_i64 1 #define TCG_TARGET_HAS_mulu2_i64 1 #define TCG_TARGET_HAS_muls2_i64 0 +extern bool tcg_target_deposit_valid(int ofs, int len); +#define TCG_TARGET_deposit_i32_valid tcg_target_deposit_valid +#define TCG_TARGET_deposit_i64_valid tcg_target_deposit_valid + /* used for function call generation */ #define TCG_REG_CALL_STACK TCG_REG_R15 #define TCG_TARGET_STACK_ALIGN 8