Patchwork [13/14] cadence_uart: Flush queued characters on reset

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Submitter Peter Maydell
Date April 5, 2013, 5:13 p.m.
Message ID <1365181999-15387-14-git-send-email-peter.maydell@linaro.org>
Download mbox | patch
Permalink /patch/234229/
State New
Headers show

Comments

Peter Maydell - April 5, 2013, 5:13 p.m.
From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>

Reset can be used to empty the rx-fifo. As the fifo full condition is
used to return false from can_receive, queued rx data should be flushed
on reset accordingly.

Cc: Wendy Liang <jliang@xilinx.com>
Cc: Jason Wu <huanyu@xilinx.com>

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reported-by: Jason Wu <huanyu@xilinx.com>
Message-id: 494c1e005e225c915d295ddfd75d992ad2dabc3c.1364964526.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/cadence_uart.c |    1 +
 1 file changed, 1 insertion(+)

Patch

diff --git a/hw/cadence_uart.c b/hw/cadence_uart.c
index 5426f10..421ec99 100644
--- a/hw/cadence_uart.c
+++ b/hw/cadence_uart.c
@@ -157,6 +157,7 @@  static void uart_rx_reset(UartState *s)
 {
     s->rx_wpos = 0;
     s->rx_count = 0;
+    qemu_chr_accept_input(s->chr);
 
     s->r[R_SR] |= UART_SR_INTR_REMPTY;
     s->r[R_SR] &= ~UART_SR_INTR_RFUL;