From patchwork Fri Apr 5 08:27:57 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Enric Balletbo i Serra X-Patchwork-Id: 234063 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id A2C302C00AD for ; Fri, 5 Apr 2013 19:28:27 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id DEE784A107; Fri, 5 Apr 2013 10:28:24 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id uSPNj7CiRSpU; Fri, 5 Apr 2013 10:28:24 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 739564A11B; Fri, 5 Apr 2013 10:28:17 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 213814A0FD for ; Fri, 5 Apr 2013 10:28:14 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id uTqyQxtre4CB for ; Fri, 5 Apr 2013 10:28:13 +0200 (CEST) X-Greylist: delayed 88134 seconds by postgrey-1.27 at theia; Fri, 05 Apr 2013 10:28:12 CEST X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-wi0-f173.google.com (mail-wi0-f173.google.com [209.85.212.173]) by theia.denx.de (Postfix) with ESMTPS id BA4A54A0FC for ; Fri, 5 Apr 2013 10:28:12 +0200 (CEST) Received: by mail-wi0-f173.google.com with SMTP id ez12so329954wid.0 for ; Fri, 05 Apr 2013 01:28:11 -0700 (PDT) X-Received: by 10.180.94.135 with SMTP id dc7mr2422760wib.11.1365150491742; Fri, 05 Apr 2013 01:28:11 -0700 (PDT) Received: from localhost.localdomain (43.Red-2-139-180.staticIP.rima-tde.net. [2.139.180.43]) by mx.google.com with ESMTPS id bo1sm2597469wib.0.2013.04.05.01.28.10 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 05 Apr 2013 01:28:11 -0700 (PDT) From: Enric Balletbo i Serra To: Date: Fri, 5 Apr 2013 10:27:57 +0200 Message-Id: <1365150478-24104-2-git-send-email-eballetbo@iseebcn.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1365150478-24104-1-git-send-email-eballetbo@iseebcn.com> References: <1365150478-24104-1-git-send-email-eballetbo@iseebcn.com> Cc: trini@ti.com, Enric Balletbo i Serra Subject: [U-Boot] [PATCHv2 1/2] Add DDR3 support for IGEP COM AQUILA/CYGNUS. X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de These boards uses Samsung K4B2G1646E-BIH9 a 2Gb E-die DDR3 SDRAM. Signed-off-by: Enric Balletbo i Serra --- arch/arm/include/asm/arch-am33xx/ddr_defs.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index 260cc34..4ebc557 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -117,6 +117,23 @@ #define MT41J512M8RH125_PHY_WR_DATA 0x74 #define MT41J512M8RH125_IOCTRL_VALUE 0x18B +/* Samsung K4B2G1646E-BIH9 */ +#define K4B2G1646EBIH9_EMIF_READ_LATENCY 0x06 +#define K4B2G1646EBIH9_EMIF_TIM1 0x0888A39B +#define K4B2G1646EBIH9_EMIF_TIM2 0x2A04011A +#define K4B2G1646EBIH9_EMIF_TIM3 0x501F820F +#define K4B2G1646EBIH9_EMIF_SDCFG 0x61C24AB2 +#define K4B2G1646EBIH9_EMIF_SDREF 0x0000093B +#define K4B2G1646EBIH9_ZQ_CFG 0x50074BE4 +#define K4B2G1646EBIH9_DLL_LOCK_DIFF 0x1 +#define K4B2G1646EBIH9_RATIO 0x40 +#define K4B2G1646EBIH9_INVERT_CLKOUT 0x1 +#define K4B2G1646EBIH9_RD_DQS 0x3B +#define K4B2G1646EBIH9_WR_DQS 0x85 +#define K4B2G1646EBIH9_PHY_FIFO_WE 0x100 +#define K4B2G1646EBIH9_PHY_WR_DATA 0xC1 +#define K4B2G1646EBIH9_IOCTRL_VALUE 0x18B + /** * Configure DMM */