From patchwork Thu Apr 4 22:56:24 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 233986 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id A78312C00A9 for ; Fri, 5 Apr 2013 10:09:57 +1100 (EST) Received: from localhost ([::1]:59500 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UNtI3-0007X1-Pp for incoming@patchwork.ozlabs.org; Thu, 04 Apr 2013 19:09:55 -0400 Received: from eggs.gnu.org ([208.118.235.92]:47759) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UNt6J-0006hc-0R for qemu-devel@nongnu.org; Thu, 04 Apr 2013 18:57:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UNt6C-0001SY-Du for qemu-devel@nongnu.org; Thu, 04 Apr 2013 18:57:46 -0400 Received: from mail-oa0-f43.google.com ([209.85.219.43]:39012) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UNt6C-0001SH-8Y for qemu-devel@nongnu.org; Thu, 04 Apr 2013 18:57:40 -0400 Received: by mail-oa0-f43.google.com with SMTP id l10so3420892oag.30 for ; Thu, 04 Apr 2013 15:57:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=qXTu4y8QAkWKWzOhBCiv/PqLSYRRce1QJTWqPJd8Axg=; b=gQMdqtS5b8xLYcwS3tqZNbj1KU2ls+e3DtXdcDhIsKsrCUvXIXZDfeoM9mW64NXEj4 obmjOr7WUjFfX/QfbRqf4RSTgh9X6aonv/9qhHf7JAMkElILc7BR8/hwxzgEDrGy/kx9 tjUwgqitrgGphfxI9BGbQPzivghbHt5eCjInM5CqNI/zuE1FcI5aWAtjManLkbphH14k xNtBLF+5QIJckAua0dMoqRA+OPi/w5iPjFIDKjvF+cJurPfM7RpldJU9CicYbssWBTnJ OPxk00AZ5XQ4+b+HWeGN7TWMgf+uMVDTecfHtQiOC6ic8c1MI9qMCOR+bGAXUWnucg0b xT8Q== X-Received: by 10.60.142.164 with SMTP id rx4mr6298372oeb.83.1365116259715; Thu, 04 Apr 2013 15:57:39 -0700 (PDT) Received: from pebble.com ([12.236.175.36]) by mx.google.com with ESMTPS id j10sm9227424obg.4.2013.04.04.15.57.38 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Thu, 04 Apr 2013 15:57:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 4 Apr 2013 17:56:24 -0500 Message-Id: <1365116186-19382-32-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1365116186-19382-1-git-send-email-rth@twiddle.net> References: <1365116186-19382-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 209.85.219.43 Cc: av1474@comtv.ru, Aurelien Jarno Subject: [Qemu-devel] [PATCH v4 31/33] tcg-ppc64: Implement add2/sub2_i64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- tcg/ppc64/tcg-target.c | 56 ++++++++++++++++++++++++++++++++++++++++++++++++++ tcg/ppc64/tcg-target.h | 4 ++-- 2 files changed, 58 insertions(+), 2 deletions(-) diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index 6dec600..b134029 100644 --- a/tcg/ppc64/tcg-target.c +++ b/tcg/ppc64/tcg-target.c @@ -27,6 +27,7 @@ #define TCG_CT_CONST_S32 0x400 #define TCG_CT_CONST_U32 0x800 #define TCG_CT_CONST_ZERO 0x1000 +#define TCG_CT_CONST_MONE 0x2000 static uint8_t *tb_ret_addr; @@ -262,6 +263,9 @@ static int target_parse_constraint (TCGArgConstraint *ct, const char **pct_str) case 'J': ct->ct |= TCG_CT_CONST_U16; break; + case 'M': + ct->ct |= TCG_CT_CONST_MONE; + break; case 'T': ct->ct |= TCG_CT_CONST_S32; break; @@ -296,6 +300,8 @@ static int tcg_target_const_match (tcg_target_long val, return 1; } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) { return 1; + } else if ((ct & TCG_CT_CONST_MONE) && val == -1) { + return 1; } return 0; } @@ -366,11 +372,15 @@ static int tcg_target_const_match (tcg_target_long val, #define EXTSW XO31(986) #define ADD XO31(266) #define ADDE XO31(138) +#define ADDME XO31(234) +#define ADDZE XO31(202) #define ADDC XO31( 10) #define AND XO31( 28) #define SUBF XO31( 40) #define SUBFC XO31( 8) #define SUBFE XO31(136) +#define SUBFME XO31(232) +#define SUBFZE XO31(200) #define OR XO31(444) #define XOR XO31(316) #define MULLW XO31(235) @@ -1935,6 +1945,49 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args, args[3], args[4], const_args[2]); break; + case INDEX_op_add2_i64: + /* Note that the CA bit is defined based on the word size of the + environment. So in 64-bit mode it's always carry-out of bit 63. + The fallback code using deposit works just as well for 32-bit. */ + a0 = args[0], a1 = args[1]; + if (a0 == args[4] || (!const_args[5] && a0 == args[5])) { + a0 = TCG_REG_R0; + } + if (const_args[3]) { + tcg_out32(s, ADDIC | TAI(a0, args[2], args[3])); + } else { + tcg_out32(s, ADDC | TAB(a0, args[2], args[3])); + } + if (const_args[5]) { + tcg_out32(s, (args[5] ? ADDME : ADDZE) | RT(a1) | RA(args[4])); + } else { + tcg_out32(s, ADDE | TAB(a1, args[4], args[5])); + } + if (a0 != args[0]) { + tcg_out_mov(s, TCG_TYPE_I64, args[0], a0); + } + break; + + case INDEX_op_sub2_i64: + a0 = args[0], a1 = args[1]; + if (a0 == args[5] || (!const_args[4] && a0 == args[4])) { + a0 = TCG_REG_R0; + } + if (const_args[2]) { + tcg_out32(s, SUBFIC | TAI(a0, args[3], args[2])); + } else { + tcg_out32(s, SUBFC | TAB(a0, args[3], args[2])); + } + if (const_args[4]) { + tcg_out32(s, (args[4] ? SUBFME : SUBFZE) | RT(a1) | RA(args[5])); + } else { + tcg_out32(s, SUBFE | TAB(a1, args[5], args[4])); + } + if (a0 != args[0]) { + tcg_out_mov(s, TCG_TYPE_I64, args[0], a0); + } + break; + default: tcg_dump_ops (s); tcg_abort (); @@ -2061,6 +2114,9 @@ static const TCGTargetOpDef ppc_op_defs[] = { { INDEX_op_deposit_i32, { "r", "0", "r" } }, { INDEX_op_deposit_i64, { "r", "0", "r" } }, + { INDEX_op_add2_i64, { "r", "r", "r", "rI", "r", "rZM" } }, + { INDEX_op_sub2_i64, { "r", "r", "rI", "r", "rZM", "r" } }, + { -1 }, }; diff --git a/tcg/ppc64/tcg-target.h b/tcg/ppc64/tcg-target.h index 67313b9..8dff1d5 100644 --- a/tcg/ppc64/tcg-target.h +++ b/tcg/ppc64/tcg-target.h @@ -112,8 +112,8 @@ typedef enum { #define TCG_TARGET_HAS_nor_i64 1 #define TCG_TARGET_HAS_deposit_i64 1 #define TCG_TARGET_HAS_movcond_i64 1 -#define TCG_TARGET_HAS_add2_i64 0 -#define TCG_TARGET_HAS_sub2_i64 0 +#define TCG_TARGET_HAS_add2_i64 1 +#define TCG_TARGET_HAS_sub2_i64 1 #define TCG_TARGET_HAS_mulu2_i64 0 #define TCG_TARGET_HAS_muls2_i64 0