From patchwork Thu Apr 4 22:55:57 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 233967 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 7CFBE2C00A3 for ; Fri, 5 Apr 2013 09:57:46 +1100 (EST) Received: from localhost ([::1]:53819 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UNt6G-0005cW-PV for incoming@patchwork.ozlabs.org; Thu, 04 Apr 2013 18:57:44 -0400 Received: from eggs.gnu.org ([208.118.235.92]:47347) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UNt5Z-0005ak-Nj for qemu-devel@nongnu.org; Thu, 04 Apr 2013 18:57:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UNt5S-0001Fi-T3 for qemu-devel@nongnu.org; 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Thu, 04 Apr 2013 15:56:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 4 Apr 2013 17:55:57 -0500 Message-Id: <1365116186-19382-5-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1365116186-19382-1-git-send-email-rth@twiddle.net> References: <1365116186-19382-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 209.85.219.47 Cc: av1474@comtv.ru, Aurelien Jarno Subject: [Qemu-devel] [PATCH v4 04/33] tcg-ppc64: Introduce and use tcg_out_ext32u X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- tcg/ppc64/tcg-target.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index 3587d0e..84e30ad 100644 --- a/tcg/ppc64/tcg-target.c +++ b/tcg/ppc64/tcg-target.c @@ -451,6 +451,11 @@ static inline void tcg_out_rlw(TCGContext *s, int op, TCGReg ra, TCGReg rs, tcg_out32(s, op | RA(ra) | RS(rs) | SH(sh) | MB(mb) | ME(me)); } +static inline void tcg_out_ext32u(TCGContext *s, TCGReg dst, TCGReg src) +{ + tcg_out_rld(s, RLDICL, dst, src, 0, 32); +} + static void tcg_out_movi32(TCGContext *s, TCGReg ret, int32_t arg) { if (arg == (int16_t) arg) @@ -484,7 +489,7 @@ static void tcg_out_movi (TCGContext *s, TCGType type, else { tcg_out_movi32 (s, ret, arg32); if (arg32 < 0) - tcg_out_rld (s, RLDICL, ret, ret, 0, 32); + tcg_out_ext32u(s, ret, ret); } } } @@ -578,7 +583,7 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg addr_reg, int s_bits, int offset) { #if TARGET_LONG_BITS == 32 - tcg_out_rld (s, RLDICL, addr_reg, addr_reg, 0, 32); + tcg_out_ext32u(s, addr_reg, addr_reg); tcg_out_rlw(s, RLWINM, r0, addr_reg, 32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS), @@ -691,7 +696,7 @@ static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc) #else /* !CONFIG_SOFTMMU */ #if TARGET_LONG_BITS == 32 - tcg_out_rld (s, RLDICL, addr_reg, addr_reg, 0, 32); + tcg_out_ext32u(s, addr_reg, addr_reg); #endif r0 = addr_reg; r1 = 3; @@ -824,7 +829,7 @@ static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc) #else /* !CONFIG_SOFTMMU */ #if TARGET_LONG_BITS == 32 - tcg_out_rld (s, RLDICL, addr_reg, addr_reg, 0, 32); + tcg_out_ext32u(s, addr_reg, addr_reg); #endif r1 = 3; r0 = addr_reg; @@ -1531,7 +1536,7 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args, break; case INDEX_op_ext32u_i64: - tcg_out_rld (s, RLDICL, args[0], args[1], 0, 32); + tcg_out_ext32u(s, args[0], args[1]); break; case INDEX_op_setcond_i32: