Patchwork [5/6] ARM: i.MX5: Add PATA and SRTC clocks

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Submitter Sascha Hauer
Date April 4, 2013, 9:25 a.m.
Message ID <1365067509-10186-6-git-send-email-s.hauer@pengutronix.de>
Download mbox | patch
Permalink /patch/233695/
State New
Headers show

Comments

Sascha Hauer - April 4, 2013, 9:25 a.m.
This adds the clock gates and the binding documentation
for PATA and SRTC.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 Documentation/devicetree/bindings/clock/imx5-clock.txt | 2 ++
 arch/arm/mach-imx/clk-imx51-imx53.c                    | 4 +++-
 2 files changed, 5 insertions(+), 1 deletion(-)
Shawn Guo - April 4, 2013, 1:13 p.m.
On Thu, Apr 04, 2013 at 11:25:08AM +0200, Sascha Hauer wrote:
> This adds the clock gates and the binding documentation
> for PATA and SRTC.
> 
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Patch #5 and #6 applied, thanks.

Patch

diff --git a/Documentation/devicetree/bindings/clock/imx5-clock.txt b/Documentation/devicetree/bindings/clock/imx5-clock.txt
index 2a0c904..da5eb30 100644
--- a/Documentation/devicetree/bindings/clock/imx5-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx5-clock.txt
@@ -172,6 +172,8 @@  clocks and IDs.
 	can1_serial_gate	157
 	can1_ipg_gate		158
 	owire_gate		159
+	srtc_gate		160
+	pata_gate		161
 
 Examples (for mx53):
 
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 0f39f8c..026a819 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -83,7 +83,7 @@  enum imx5_clks {
 	ssi2_root_gate, ssi3_root_gate, ssi_ext1_gate, ssi_ext2_gate,
 	epit1_ipg_gate, epit1_hf_gate, epit2_ipg_gate, epit2_hf_gate,
 	can_sel, can1_serial_gate, can1_ipg_gate,
-	owire_gate,
+	owire_gate, srtc_gate, pata_gate,
 	clk_max
 };
 
@@ -235,6 +235,8 @@  static void __init mx5_clocks_common_init(unsigned long rate_ckil,
 	clk[epit2_ipg_gate] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6);
 	clk[epit2_hf_gate] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8);
 	clk[owire_gate] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22);
+	clk[srtc_gate] = imx_clk_gate2("srtc_gate", "per_root", MXC_CCM_CCGR4, 28);
+	clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", MXC_CCM_CCGR4, 0);
 
 	for (i = 0; i < ARRAY_SIZE(clk); i++)
 		if (IS_ERR(clk[i]))