From patchwork Wed Apr 3 23:17:12 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom Warren X-Patchwork-Id: 233597 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 6A2B52C010B for ; Thu, 4 Apr 2013 10:18:12 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 27D854A2FB; Thu, 4 Apr 2013 01:18:11 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id IzsSqn3FMRgJ; Thu, 4 Apr 2013 01:18:11 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E99524A2FE; Thu, 4 Apr 2013 01:18:09 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 74F904A2FE for ; Thu, 4 Apr 2013 01:18:07 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id TSF-TsBgLN2o for ; Thu, 4 Apr 2013 01:18:05 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pb0-f51.google.com (mail-pb0-f51.google.com [209.85.160.51]) by theia.denx.de (Postfix) with ESMTPS id 0F4834A2FB for ; Thu, 4 Apr 2013 01:18:03 +0200 (CEST) Received: by mail-pb0-f51.google.com with SMTP id rr4so1105835pbb.10 for ; Wed, 03 Apr 2013 16:18:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer :x-nvconfidentiality; bh=Xggcjct9TdOvFTULXsqSuSeed1hk3bKKg4S/LXNqnLE=; b=amJmkLJfbeh5er2hBnwhkNgTGl2GiiVEc22/R0mp9lw9gQJ6tJeacSVQlUI4Z0JwB4 /LslbDuJ01G82r8UyV04eG7zsh8pjdKH4fEu0kgOi+YNXMjFH7he0GpvMWXlbetDhh5u J7eLyTid7JOUk1RlA2UYvHJ67Khxuome5bcoc9JFrHTkR2xbKR7xVJ6GpUVcDT1FA2XQ fGK6FPa7CbRuesvcL6D9QuQixQ9bkqZG3k6fkA07gGgi211+jqNTfcwLSiY5Zz7lesy7 vwFKUO+FmSCE7Ip8DNm8XewnFgeMvxy9Vk6UjXPrVbpQ0FREH6+QGOXyMgGdI84vJcQ1 3HHQ== X-Received: by 10.68.175.1 with SMTP id bw1mr5411518pbc.140.1365031082019; Wed, 03 Apr 2013 16:18:02 -0700 (PDT) Received: from localhost.localdomain (ip68-230-103-25.ph.ph.cox.net. [68.230.103.25]) by mx.google.com with ESMTPS id hs8sm7614139pbc.27.2013.04.03.16.17.59 (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 03 Apr 2013 16:18:00 -0700 (PDT) From: Tom Warren To: u-boot@lists.denx.de Date: Wed, 3 Apr 2013 16:17:12 -0700 Message-Id: <1365031032-12739-1-git-send-email-twarren@nvidia.com> X-Mailer: git-send-email 1.8.1.5 X-NVConfidentiality: public Cc: swarren@nvidia.com, Tom Warren , twarren.nvidia@gmail.com Subject: [U-Boot] [PATCH] Tegra: Fix MSELECT clock divisors for T30/T114. X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de A comparison of registers between our internal NV U-Boot and u-boot-tegra/next showed some discrepancies in the MSELECT clock divisor programming. T20 doesn't have a MSELECT clk src reg. Signed-off-by: Tom Warren Reviewed-by: Stephen Warren --- arch/arm/cpu/arm720t/tegra114/cpu.c | 10 ++++------ arch/arm/cpu/arm720t/tegra30/cpu.c | 4 ++-- 2 files changed, 6 insertions(+), 8 deletions(-) diff --git a/arch/arm/cpu/arm720t/tegra114/cpu.c b/arch/arm/cpu/arm720t/tegra114/cpu.c index 6a94179..51ecff7 100644 --- a/arch/arm/cpu/arm720t/tegra114/cpu.c +++ b/arch/arm/cpu/arm720t/tegra114/cpu.c @@ -170,15 +170,13 @@ void t114_init_clocks(void) clock_set_enable(PERIPH_ID_MC1, 1); clock_set_enable(PERIPH_ID_DVFS, 1); - /* Switch MSELECT clock to PLLP (00) */ - clock_ll_set_source(PERIPH_ID_MSELECT, 0); - /* - * Clock divider request for 102MHz would setup MSELECT clock as - * 102MHz for PLLP base 408MHz + * Set MSELECT clock source as PLLP (00), and ask for a clock + * divider that would set the MSELECT clock at 102MHz for a + * PLLP base of 408MHz. */ clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0, - (NVBL_PLLP_KHZ/102000)); + CLK_DIVIDER(NVBL_PLLP_KHZ, 102000)); /* I2C5 (DVC) gets CLK_M and a divisor of 17 */ clock_ll_set_source_divisor(PERIPH_ID_I2C5, 3, 16); diff --git a/arch/arm/cpu/arm720t/tegra30/cpu.c b/arch/arm/cpu/arm720t/tegra30/cpu.c index dedcdd9..e162357 100644 --- a/arch/arm/cpu/arm720t/tegra30/cpu.c +++ b/arch/arm/cpu/arm720t/tegra30/cpu.c @@ -110,8 +110,8 @@ void t30_init_clocks(void) reset_set_enable(PERIPH_ID_MSELECT, 1); clock_set_enable(PERIPH_ID_MSELECT, 1); - /* Switch MSELECT clock to PLLP (00) */ - clock_ll_set_source(PERIPH_ID_MSELECT, 0); + /* Switch MSELECT clock to PLLP (00) and use a divisor of 2 */ + clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0, 2); /* * Our high-level clock routines are not available prior to