Patchwork [U-Boot] Tegra114: Initialize System Counter (TSC) with osc frequency

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Submitter Tom Warren
Date April 3, 2013, 11:12 p.m.
Message ID <1365030744-12562-1-git-send-email-twarren@nvidia.com>
Download mbox | patch
Permalink /patch/233596/
State Accepted
Delegated to: Tom Warren
Headers show

Comments

Tom Warren - April 3, 2013, 11:12 p.m.
T114 needs the SYSCTR0 counter initialized so the TSC can be
read by the kernel. Do it in the bootloader since it's a write-once
deal (secure/non-secure mode dependent).

Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 arch/arm/cpu/tegra-common/clock.c           |  3 +++
 arch/arm/cpu/tegra114-common/clock.c        | 22 ++++++++++++++++++
 arch/arm/cpu/tegra20-common/clock.c         |  4 ++++
 arch/arm/cpu/tegra30-common/clock.c         |  4 ++++
 arch/arm/include/asm/arch-tegra/clock.h     |  3 +++
 arch/arm/include/asm/arch-tegra114/sysctr.h | 35 +++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-tegra114/tegra.h  |  1 +
 7 files changed, 72 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-tegra114/sysctr.h
Stephen Warren - April 3, 2013, 11:26 p.m.
On 04/03/2013 05:12 PM, Tom Warren wrote:
> T114 needs the SYSCTR0 counter initialized so the TSC can be
> read by the kernel. Do it in the bootloader since it's a write-once
> deal (secure/non-secure mode dependent).

> diff --git a/arch/arm/cpu/tegra-common/clock.c b/arch/arm/cpu/tegra-common/clock.c

> @@ -557,4 +557,7 @@ void clock_init(void)
...
> +	/* Do any special system timer/TSC setup */
> +	arch_timer_init();

I wonder if we shouldn't ifdef that, so that ...

> diff --git a/arch/arm/cpu/tegra20-common/clock.c b/arch/arm/cpu/tegra20-common/clock.c

> +void arch_timer_init(void)
> +{
> +}

We don't need those stubs on the chips that don't support this. (I
imagine that for future chips, the implementation will be common and
will move out of the chip-specific file into some arch-timers file).

Either way though,
Reviewed-by: Stephen Warren <swarren@nvidia.com>

Patch

diff --git a/arch/arm/cpu/tegra-common/clock.c b/arch/arm/cpu/tegra-common/clock.c
index 49a0633..9156d00 100644
--- a/arch/arm/cpu/tegra-common/clock.c
+++ b/arch/arm/cpu/tegra-common/clock.c
@@ -557,4 +557,7 @@  void clock_init(void)
 	debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]);
 	debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]);
 	debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]);
+
+	/* Do any special system timer/TSC setup */
+	arch_timer_init();
 }
diff --git a/arch/arm/cpu/tegra114-common/clock.c b/arch/arm/cpu/tegra114-common/clock.c
index 9b29ce1..5c4305a 100644
--- a/arch/arm/cpu/tegra114-common/clock.c
+++ b/arch/arm/cpu/tegra114-common/clock.c
@@ -19,6 +19,7 @@ 
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
+#include <asm/arch/sysctr.h>
 #include <asm/arch/tegra.h>
 #include <asm/arch-tegra/clk_rst.h>
 #include <asm/arch-tegra/timer.h>
@@ -653,3 +654,24 @@  void clock_early_init(void)
 	writel(0x40000C10, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc);
 	udelay(2);
 }
+
+void arch_timer_init(void)
+{
+	struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;
+	u32 freq, val;
+
+	freq = clock_get_rate(CLOCK_ID_OSC);
+	debug("%s: osc freq is %dHz [0x%08X]\n", __func__, freq, freq);
+
+	/* ARM CNTFRQ */
+	asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
+
+	/* Only T114 has the System Counter regs */
+	debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq);
+	writel(freq, &sysctr->cntfid0);
+
+	val = readl(&sysctr->cntcr);
+	val |= TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG;
+	writel(val, &sysctr->cntcr);
+	debug("%s: TSC CNTCR = 0x%08X\n", __func__, val);
+}
diff --git a/arch/arm/cpu/tegra20-common/clock.c b/arch/arm/cpu/tegra20-common/clock.c
index ec93894..4afb205 100644
--- a/arch/arm/cpu/tegra20-common/clock.c
+++ b/arch/arm/cpu/tegra20-common/clock.c
@@ -559,3 +559,7 @@  void clock_early_init(void)
 		break;
 	}
 }
+
+void arch_timer_init(void)
+{
+}
diff --git a/arch/arm/cpu/tegra30-common/clock.c b/arch/arm/cpu/tegra30-common/clock.c
index a93f2c9..74bd22b 100644
--- a/arch/arm/cpu/tegra30-common/clock.c
+++ b/arch/arm/cpu/tegra30-common/clock.c
@@ -616,3 +616,7 @@  void clock_early_init(void)
 		break;
 	}
 }
+
+void arch_timer_init(void)
+{
+}
diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h
index c8677bd..c7a696c 100644
--- a/arch/arm/include/asm/arch-tegra/clock.h
+++ b/arch/arm/include/asm/arch-tegra/clock.h
@@ -317,4 +317,7 @@  int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon);
 #define periphc_internal_id_isvalid(id) ((id) >= 0 && \
 		(id) < PERIPHC_COUNT)
 
+/* SoC-specific TSC init */
+void arch_timer_init(void);
+
 #endif  /* _TEGRA_CLOCK_H_ */
diff --git a/arch/arm/include/asm/arch-tegra114/sysctr.h b/arch/arm/include/asm/arch-tegra114/sysctr.h
new file mode 100644
index 0000000..c05e2c3
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra114/sysctr.h
@@ -0,0 +1,35 @@ 
+/*
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA114_SYSCTR_H_
+#define _TEGRA114_SYSCTR_H_
+
+struct sysctr_ctlr {
+	u32 cntcr;		/* 0x00: SYSCTR0_CNTCR Counter Control */
+	u32 cntsr;		/* 0x04: SYSCTR0_CNTSR Counter Status */
+	u32 cntcv0;		/* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */
+	u32 cntcv1;		/* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */
+	u32 reserved1[4];	/* 0x10 - 0x1C */
+	u32 cntfid0;		/* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */
+	u32 cntfid1;		/* 0x24: SYSCTR0_CNTFID1 Freq Table End */
+	u32 reserved2[1002];	/* 0x28 - 0xFCC */
+	u32 counterid[12];	/* 0xFD0 - 0xFxx CounterID regs, RO */
+};
+
+#define TSC_CNTCR_ENABLE	(1 << 0)	/* Enable */
+#define TSC_CNTCR_HDBG		(1 << 1)	/* Halt on debug */
+
+#endif	/* _TEGRA114_SYSCTR_H_ */
diff --git a/arch/arm/include/asm/arch-tegra114/tegra.h b/arch/arm/include/asm/arch-tegra114/tegra.h
index a3d12d6..5d426b5 100644
--- a/arch/arm/include/asm/arch-tegra114/tegra.h
+++ b/arch/arm/include/asm/arch-tegra114/tegra.h
@@ -18,6 +18,7 @@ 
 #define _TEGRA114_H_
 
 #define NV_PA_SDRAM_BASE	0x80000000	/* 0x80000000 for real T114 */
+#define NV_PA_TSC_BASE		0x700F0000	/* System Counter TSC regs */
 
 #include <asm/arch-tegra/tegra.h>